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参数资料
| 型号： | ICSSSTV16857CL-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封装： | 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48 |
| 文件页数： | 4/9页 |
| 文件大小： | 220K |
| 代理商： | ICSSSTV16857CL-T |
4
ICSSSTV16857C
0002F—10/25/02
Electrical Characteristics - DC
TA = 0 - 70 C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
VDDQ
MIN
TYP
MAX
UNITS
VIK
II = -18mA
2.3V
-1.2
IOH = -100A
2.3V-2.7V
VDDQ -
0.2
IOH = -16mA
2.3V
1.95
IOL = 100A
2.3V-2.7V
0.2
IOL = 16mA
2.3V
0.35
II
All Inputs
VI = VDD or GND
2.7V
±5
A
Standby (Static)
RESET# = GND
0.01
A
Operating (Static)
VI = VIH(AC) or VIL(AC),
RESET# = VDD
52
mA
Dynamic operating
(clock only)
RESET# = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLK# switching
50% duty cycle.
75
A/clock
MHz
Dynamic Operating
(per each data input)
RESET# = VDD,
VI = VIH(AC) or VIL (AC),
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
15
A/ clock
MHz/data
rOH
Output High
2.3V-2.7V
7
13.5
20
rOL
Output Low
2.3V-2.7V
7
13
20
rO(D)
[rOH - rOL] each
separate bit
2.5V
4
Data Inputs
2.5
3.5
CLK and CLK#
2.5
3.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
Ci
IOL = 20mA
IO = 20mA, TA = 25° C
VOH
VOL
IDD
IDDD
IO = 0
CONDITIONS
2.7V
2.5V
VI = VREF ±350mV
VICR = 1.25V, VI(PP) = 360mV
pF
IOH = -20mA
V
ICSSSTV16857C
DDR 14-Bit Registered Buffer
TSD
IDT / ICS DDR 14-Bit Registered Buffer
ICSSSTV16857C
4
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| ICSSSTV16859YG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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