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参数资料
| 型号： | ICSSSTV16857CL-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封装： | 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48 |
| 文件页数： | 5/9页 |
| 文件大小： | 220K |
| 代理商： | ICSSSTV16857CL-T |
5
ICSSSTV16857C
0002F—10/25/02
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
MIN
TYP
MAX
fmax
200
MHz
tPD
CLK, CLK#
Q
1.7
2.1
2.5
ns
tphl
RESET#
Q
3.5
ns
SYMBOL
VDD = 2.5V ±0.2V
UNITS
From
(Input)
To
(Output)
Timing Requirements
1
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
fclock
Clock frequency
200
MHz
tPD
Clock to output time
1.7
2.5
ns
tRST
Reset to output time
3.5
ns
tSL
Output slew rate
1
4
V/ns
Setup time, fast slew rate
2 & 4
0.4
ns
Setup time, slow slew rate
3 & 4
0.5
ns
Hold time, fast slew rate
2 & 4
0.4
ns
Hold time, slow slew rate
3 & 4
0.5
ns
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate
≥ 1V/ns.
3 - For data signal input slew rate
≥ 0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rates are
≥ 1V/ns.
UNITS
Th
VDDQ = 2.5±0.2V
tS
Data before CLK
↑ , CLK#↓
Data after CLK
↑ , CLK#↓
SYMBOL
PARAMETERS
ICSSSTV16857C
DDR 14-Bit Registered Buffer
TSD
IDT / ICS DDR 14-Bit Registered Buffer
ICSSSTV16857C
5
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相关代理商/技术参数 |
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| ICSSSTV16857YG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
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| ICSSSTV16859YG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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