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参数资料
| 型号： | ICSSSTV16859YKLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC56 |
| 封装： | VFQFN-56 |
| 文件页数： | 2/8页 |
| 文件大小： | 91K |
| 代理商： | ICSSSTV16859YKLF |
2
ICSSSTV16859
0003G—05/21/02
General Description
Pin Configuration (64-Pin TSSOP)
The 13-bit-to-26-bit ICSSSTV16859 is a universal bus driver designed for 2.3V to 2.7V VDD operation and
SSTL_2 I/O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The
positive edge of CLK is used to trigger the data flow whereas CLK# is used to maintain sufficient noise margins
where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only.
ICSSSTV16859 supports low-power standby operation. A logic level “Low” at RESET# assures that all internal
registers and outputs (Q) are reset to the logic “Low” state, and all input receivers, data (D) and clock (CLK/
CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid
logic state because VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be
held at a logic “low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and
CLK#. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power
standby state, the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative
to the time to disable the differential input receivers. This ensures there are no glitches on the output. However,
when coming out of low-power standby state, the register will become active quickly relative to the time to
enable the differential input receivers. When the data inputs are at a logic level “low” and the clock is stable
during the “Low”-to-”High” transition of RESET# until the input receivers are fully enabled, the design ensures
that the outputs will remain at a logic “Low” level.
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Pin Configuration (56-Pin MLF2)
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相关代理商/技术参数 |
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| ICSSSTV32852 | 制造商:ICS 制造商全称:ICS 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
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