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参数资料
| 型号： | ICSVF2510YG-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24 |
| 文件页数： | 2/7页 |
| 文件大小： | 95K |
| 代理商： | ICSVF2510YG-T |
2
ICSVF2510
0722B—05/06/04
Pin Descriptions
Note:
1.
Weak pull-ups on these inputs
Functionality
PIN #
PIN NAME
TYPE
DESCRIPTION
1
AGND
PWR
Analog Ground
2, 10, 14
VCC
PWR
Power Supply (3.3V)
3
CLK0
OUT
Buffered clock output.
4
CLK1
OUT
Buffered clock output.
5
CLK2
OUT
Buffered clock output.
6, 7, 18, 19
GND
PWR
Ground
8
CLK3
OUT
Buffered clock output.
9
CLK4
OUT
Buffered clock output.
11
OE
1
IN
Output enable (has internal pull_up). When high, normal operation.
When low, clock outputs are disabled to a logic low state.
12
FBOUT
OUT
Feedback output
13
FBIN
IN
Feedback input
15
CLK5
OUT
Buffered clock output.
16
CLK6
OUT
Buffered clock output.
17
CLK7
OUT
Buffered clock output.
20
CLK8
OUT
Buffered clock output.
21
CLK9
OUT
Buffered clock output.
22
VCC
PWR
Power Supply (3.3V) digital supply.
23
AVCC
IN
Analog power supply (3.3V). When input is ground PLL is off and
bypassed.
24
CLKIN
IN
Clock input
OE
AVCC
CLK (9:0)
FBOUT
Source
03.33
0
Driven
PLL
N
1
3.33
Driven
PLL
N
00
0
Driven
CLKIN
Y
10
Driven
CLKIN
Y
Test mode:
When AVCC is 0, shuts off the PLL
and connects the input directly to the output buffers
Buffer Mode
INPUTS
OUTPUTS
PLL
Shutdown
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相关代理商/技术参数 |
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| ICSXXXXCFLFT | 制造商:ICS 制造商全称:ICS 功能描述:PCIe Gen 2 main Clock for Intel-based Servers |
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| ICSXXXXY | 制造商:ICS 制造商全称:ICS 功能描述:Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| ICSXXXXYFLFT | 制造商:ICS 制造商全称:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
| ICSXXXXYGLFT | 制造商:ICS 制造商全称:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
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