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参数资料
| 型号： | ICSVF2510YG-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24 |
| 文件页数： | 4/7页 |
| 文件大小： | 95K |
| 代理商： | ICSVF2510YG-T |
4
ICSVF2510
0722B—05/06/04
Electrical Characteristics - Input & Supply
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
0.1
100
uA
Input Low Current
IIL
VIN = 0 V;
19
50
uA
Operating current
IDD
1
CL = 0 pF; FIN @ 66MHz
170
mA
Input Capacitance
CIN
1
Logic Inputs
4
pF
1Guaranteed by design, not 100% tested in production.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
FOP
Operating frequency
20
200
MHz
FCLK
Input clock
frequency
25
200
MHz
Input clock
frequency duty
cycle
40
60
%
Stabilization time
After power up
15
s
Timing requirements over recommended ranges of supply
voltage and operating free-air temperature
Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal.
In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK.
Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not applicable.
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相关代理商/技术参数 |
参数描述 |
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| ICSXXXXCFLFT | 制造商:ICS 制造商全称:ICS 功能描述:PCIe Gen 2 main Clock for Intel-based Servers |
| ICSXXXXCGLFT | 制造商:ICS 制造商全称:ICS 功能描述:PCIe Gen 2 main Clock for Intel-based Servers |
| ICSXXXXY | 制造商:ICS 制造商全称:ICS 功能描述:Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| ICSXXXXYFLFT | 制造商:ICS 制造商全称:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
| ICSXXXXYGLFT | 制造商:ICS 制造商全称:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
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