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参数资料
| 型号： | ICSVF2510YG-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24 |
| 文件页数： | 7/7页 |
| 文件大小： | 95K |
| 代理商： | ICSVF2510YG-T |
7
ICSVF2510
0722B—05/06/04
Ordering Information
ICSVF2510yGLF-T
4.40 mm. Body, 0.65 mm. pitch TSSOP
(173 mil)
(0.0256 Inch)
MIN
MAX
MIN
MAX
A
--
1.20
--
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.19
0.30
.007
.012
c
0.09
0.20
.0035
.008
D
E
E1
4.30
4.50
.169
.177
e
L
0.45
0.75
.018
.030
N
α
0°
8°
0°
8°
aaa
--
0.10
--
.004
VARIATIONS
MIN
MAX
MIN
MAX
24
7.70
7.90
.303
.311
10-0035
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
6.40 BASIC
0.252 BASIC
0.65 BASIC
0.0256 BASIC
SEE VARIATIONS
N
D mm.
D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1
E
α
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa C
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y G LF- T
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| IDM29908JC | S SERIES, QUAD POSITIVE EDGE TRIGGERED D LATCH, TRUE OUTPUT, CDIP16 |
| IDT2305NZ-1HDCG | 2305 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| IDT2305NZ-1HDCI | 2305 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSXXXXCFLFT | 制造商:ICS 制造商全称:ICS 功能描述:PCIe Gen 2 main Clock for Intel-based Servers |
| ICSXXXXCGLFT | 制造商:ICS 制造商全称:ICS 功能描述:PCIe Gen 2 main Clock for Intel-based Servers |
| ICSXXXXY | 制造商:ICS 制造商全称:ICS 功能描述:Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| ICSXXXXYFLFT | 制造商:ICS 制造商全称:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
| ICSXXXXYGLFT | 制造商:ICS 制造商全称:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
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