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参数资料
| 型号： | IDT59920A-2SO8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 0.300 INCH, SOIC-24 |
| 文件页数： | 4/6页 |
| 文件大小： | 52K |
| 代理商： | IDT59920A-2SO8 |
4
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
INPUT TIMING REQUIREMENTS
Symbol
Description(1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
—
10
ns/V
tPWC
Input clock pulse, HIGH or LOW
3
—
ns
DH
Input duty cycle
10
90
%
REF
ReferenceClockInput
15
100
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT59920A-2
IDT59920A-5
IDT59920A-7
Symbol Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
FS = LOW
15
—
35
15
—
35
15
—
35
FREF
REF Frequency Range
FS = MED
25
—
60
25
—
60
25
—
60
MHz
FS = HIGH
40
—
100
40
—
100
40
—
100
tRPWH
REF Pulse Width HIGH(1,8)
3—
—
3
—
3
—
ns
tRPWL
REF Pulse Width LOW(1,8)
3—
—
3
—
3
—
ns
tSKEW0
Zero Output Skew (All Outputs)(1,3,4)
—
0.1
0.25
—
0.25
0.5
—
0.3
0.75
ns
tDEV
Device-to-Device Skew(1,2,5)
—
0.75
—
1.25
—
1.65
ns
tPD
REF Input to FB Propagation Delay(1,7)
0.25
0
0.25
0.5
0
0.5
0.7
0
0.7
ns
tODCV
Output Duty Cycle Variation from 50%(1)
0.5
0
0.5
1.2
0
1.2
1.5
0
1.5
ns
tORISE
OutputRiseTime(1)
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tOFALL
OutputFallTime(1)
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tLOCK
PLL Lock Time(1,6)
—
0.5
—
0.5
—
0.5
ms
tJR
Cycle-to-CycleOutputJitter(1)
RMS
—
25
—
25
—
25
ps
Peak-to-Peak
—
200
—
200
—
200
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz. Guaranteed by design and characterization, not subject to production testing.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. tSKEW is the skew between all outlets. See AC TEST LOADS.
4. For IDT59920A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.45ns Max.
5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.)
6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
7. tPD is measured with REF input rise and fall times (from 0.2VDD to 0.8VDD ) of 1.5ns.
8. Refer to INPUT TIMING REQUIREMENTS for more detail.
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