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参数资料
| 型号： | IDT59920A-2SO8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 0.300 INCH, SOIC-24 |
| 文件页数： | 5/6页 |
| 文件大小： | 52K |
| 代理商： | IDT59920A-2SO8 |
5
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
100
Outpu t
VDD
C L
C L = 50pF (C L = 30pF for -2 and -5 de vice s)
tOR ISE
tOFAL L
0.8 V DD
0.2 V DD
≤ 1.5ns
80%
20%
0V
Vth = 0.5V DD
VDD
100
RE F
FB
Q
OTH ER Q
tREF
tPD
tSKEW
tJR
tOD CV
tRPW H
tRPW L
AC TEST LOADS AND WAVEFORMS
Test Load
CMOS Input Test Waveform
CMOS Output Waveform
AC TIMING DIAGRAM
NOTES:
Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5) and terminated with VDD/2.
tSKEW:
The skew between all outputs.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.)
tODCV:
The deviation of the output from a 50% duty cycle.
tORISE and tOFALL are measured between 0.2VDD and 0.8VDD.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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