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参数资料
| 型号： | IDT5T93GL04PGI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5T SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | TSSOP-24 |
| 文件页数： | 8/14页 |
| 文件大小： | 147K |
| 代理商： | IDT5T93GL04PGI8 |
INDUSTRIALTEMPERATURERANGE
IDT5T93GL04
2.5VLVDS1:4GLITCHLESSCLOCKBUFFERTERABUFFERII
3
PIN DESCRIPTION
Symbol
I/O
Type
Description
A[1:2]
I
Adjustable(1,4) Clock input. A[1:2] is the "true" side of the differential clock input.
A[1:2]
I
Adjustable(1,4) Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the
desiredtogglevoltageforA[1:2]:
3.3V LVTTL VREF = 1650mV
2.5V LVTTL VREF = 1250mV
G
I
LVTTL
Gate control for differential outputs Q1 and Q1 through Q4 and Q4. When Gis LOW, the differential outputs are active. When Gis
HIGH, the differential outputs are asynchronously driven to the level designated by GL(2).
GL
I
LVTTL
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"
outputsdisableLOWand"complementary"outputsdisableHIGH.
Qn
O
LVDS
Clockoutputs
Qn
O
LVDS
Complementaryclockoutputs
SEL
I
LVTTL
Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1.
PD
I
LVTTL
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both
"true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3)
FSEL
I
LVTTL
At a rising edge, FSEL forces select to the input designated by SEL. Set LOW for normal operation.
VDD
PWR
Power supply for the device core and inputs
GND
PWR
Ground
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
pulses or be able to tolerate them in down stream circuitry.
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-
up after asserting PD.
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
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| IDT5T93GL061PFGI | 功能描述:IC CLOCK BUFFER MUX 2:6 32-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:TERABUFFER™ II 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| IDT5T93GL061PFGI8 | 功能描述:IC CLOCK BUFFER MUX 2:6 32-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:TERABUFFER™ II 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| IDT5T93GL06NLGI | 功能描述:IC CLK BUFFER MUX 2:6 28-VFQFPN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:TERABUFFER™ II 产品培训模块:High Bandwidth Product Overview 标准包装:1,000 系列:Precision Edge® 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:4 差分 - 输入:输出:是/是 输入:CML，LVDS，LVPECL 输出:CML 频率 - 最大:2.5GHz 电源电压:2.375 V ~ 2.625 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) |
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