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参数资料
| 型号： | IDT5T9890NLI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
| 封装： | PLASTIC, VFQFPN-68 |
| 文件页数： | 37/37页 |
| 文件大小： | 277K |
| 代理商： | IDT5T9890NLI8 |
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INDUSTRIALTEMPERATURERANGE
IDT5T9890
EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER
EXTERNALDIFFERENTIALFEEDBACK
By providing a dedicated external differential feedback, the IDT5T9890
gives users flexibility with regard to divide selection. The FB and FB/
VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0]
signals at the phase detector in order to drive the VCO. Phase differ-
ences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
Output skew with respect to the REF[1:0] and REF[1:0]/VREF[1:0] input is adjustable to compensate for PCB trace delays, backplane propagation
delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit
(tU) which ranges from 250ps to 1.25ns (see Programmable Skew Range and Resolution Table). There are 18 skew/divide configurations
available for each output pair. These configurations are chosen through JTAG/I2C programming.
PROGRAMMABLESKEW
Bit 60 = 0
Bit 60 = 1
Comments
TimingUnitCalculation(tU)
1/(16 x FNOM)
VCO Frequency Range (FNOM)(1,2)
50 to 125MHz
100 to 250MHz
SkewAdjustmentRange(3)
Max Adjustment:
±8.75ns
±4.375ns
ns
±157.5°
PhaseDegrees
±43.75%
% of Cycle Time
Example 1, FNOM = 50MHz
tU = 1.25ns
—
Example 2, FNOM = 75MHz
tU = 0.833ns
—
Example 3, FNOM = 100MHz
tU = 0.625ns
Example 4, FNOM = 150MHz
—
tU = 0.417ns
Example 5, FNOM = 200MHz
—
tU = 0.313ns
Example 6, FNOM = 250MHz
—
tU = 0.25ns
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The VCO frequency always appears at nQ[1:0] outputs when they are operated in their undivided modes. The frequency appearing at the REF[1:0] and REF[1:0]/VREF[1:0] and
FB and FB/VREF2 inputs will be FNOM when the QFB and QFB are undivided and FB divide-by-1. The frequency of the REF[1:0] and REF[1:0]/VREF[1:0] and FB and FB/VREF2
inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided QFB and QFB and setting FB divide-by-1. Using the FB divide-
by-N configuration inputs allows a different method for frequency multiplication (see JTAG/I2C Serial Configurations: FB Divide-by-N).
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed QFB and QFB output is used for feedback, then adjustment range will be greater.
For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’
range applies to all output pairs where ±7tU skew adjustment is possible and at the lowest FNOM value.
INPUT/OUTPUT SELECTION(1)
Input
Output(2)
2.5V LVTTL SE
2.5VLVTTL,
1.8V LVTTL SE
1.8VLVTTL,
2.5V LVTTL DSE
HSTL,
1.8V LVTTL DSE
eHSTL
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
NOTES:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations
of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require
the REF[1:0] /VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended
(DSE) is for single-ended operation in differential mode, requiring VREF[1:0] and VREF2.
Differential (DIF) inputs are used only in differential mode.
2. For each output bank.
MASTER RESET FUNCTIONALITY
The IDT5T9890 performs a reset of the internal output divide circuitry
when all five output banks are disabled by toggling the nSOE pins
HIGH. When one or more banks of outputs are enabled by toggling the
nSOE LOW (if the corresponding nSOE programming bits are also set
LOW), the divide circuitry starts again from a known state. In the case
that the FB output is selected for divide-by-2 or divide-by-4, the FB
output will stop toggling while all five nSOE pins and bits are LOW, and
loss of lock will occur.
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