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参数资料
| 型号： | IDT5T9955BFGI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA96 |
| 封装： | GREEN, FBGA-96 |
| 文件页数： | 2/11页 |
| 文件大小： | 137K |
| 代理商： | IDT5T9955BFGI8 |
10
INDUSTRIALTEMPERATURERANGE
IDT5T9955
2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
AC TIMING DIAGRAM
NOTES:
PE:
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated
with 75
Ω to VDDQ/2.
tSKEWPR:
The skew between a pair of outputs (xnQ0 and xnQ1) when all eight outputs are selected for 0tU.
tSKEWB:
The skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU.
tSKEW0:
The skew between outputs when they are selected for 0tU.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
tODCV:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 1.7V.
tPWL is measured at 0.7V.
tORISE and tOFALL are measured between 0.7V and 1.7V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
REF
FB
Q
OTHER Q
INVERTED Q
REF DIVIDED BY 2
REF DIVIDED BY 4
tREF
tSKEW2
tSKEW3, 4
tSKEW1, 3, 4
tSKEW2, 4
tSKEW3, 4
tSKEW2
tSKEWPR, B
tSKEW0, 1
tCCJ1-3,
4-6, 8-12
tODCV
tRPWH
tRPWL
tSKEWPR, B
tSKEW0, 1
t(φ)
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