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参数资料
| 型号： | IDT5V49EE704NDGI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 28/29页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 200MHZ 28VFQFPN |
| 产品培训模块： | VersaClock™ III Programmable Clocks |
| 特色产品： | VersaClock III Timing Devices |
| 标准包装： | 2,500 |
| 系列： | VersaClock™ III |
| 类型： | 时钟发生器，多路复用器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，LVTTL，晶体 |
| 输出： | LVCMOS，LVTTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:7 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-VFQFPN（4x4） |
| 包装： | 带卷 (TR) |
| 其它名称： | IDT5V49EE704DLGI8 IDT5V49EE704DLGI8-ND |
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IDT5V49EE704
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
8
IDT5V49EE704
REV M 092412
SS_OFFSET[5:0]
These bits are used to program the fractional offset with
respect to the nominal M integer value. For center spread,
the SS_OFFSET is set to '0' so that the spread spectrum
waveform is centered about the nominal M (Mnom) value.
For down spread, the SS_OFFSET > '0' such the spread
spectrum waveform is centered about the (Mideal -1
+SS_Offset) value. The downspread percentage can be
thought of in terms of center spread. For example, a
downspread of -1% can also be considered as a center
spread of ±0.5% but with Mnom shifted down by one and
offset. The SS_OFFSET has integer values ranging from 0
to 63.
SD[3:0]
These bits are used to shape the profile of the spread
spectrum waveform. These are delta-encoded samples of
the waveform. There are twelve sets of SD samples. The
NSSC bits determine how many of these samples are used
for the waveform. The sum of these delta-encoded samples
(sigma delta- encoded samples) determine the amount of
spread and should not exceed (63 - SS_OFFSET). The
maximum spread is inversely proportional to the nominal M
integer value.
DITH
This bit is used for dithering the sigma-delta-encoded
samples. This will randomize the least-significant bit of the
input to the spread spectrum modulator. Set the
bit to '1' to
enable dithering.
X2
This bit will double the total value of the
sigma-delta-encoded-samples which will increase the
amplitude of the spread spectrum waveform by a factor of
two. When X2 is '0', the amplitude remains nominal but if set
to '1', the amplitude is increased by x2. The following
equations govern how the spread spectrum is set:
TSSC = TSSC[3:0] + 2 (Eq. 2)
NSSC = NSSC[2:0] * 2 (Eq. 3)
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 4)
where SJ is the unencoded sample out of a possible 12 and
SDK is the delta-encoded sample out of a possible 12.
Amplitude = ((2*N[11:0] + A[3:0] + 1) * Spread% / 100) /2
(Eq. 5)
if 1 < Amplitude < 2, then set X2 bit to '1'.
Modulation frequency:
FPFD = FIN / D (Eq. 6)
FVCO = FPFD * MNOM (Eq. 7)
FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 8)
Spread:
ΣΔ = SD0 + SD1 + SD2 + …+ SD11
the number of samples used depends on the NSSC value
ΣΔ< 63 - SS_OFFSET
±Spread% =
(
ΣΔ * 100)/(64 * (2*N[11:0] + A[3:0] + 1) (Eq. 9)
±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)
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| IDT5V49EE901-064PGGI | 制造商:Integrated Device Technology Inc 功能描述:IC PLL CLK GEN 500MHZ 24VQFN |
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| IDT5V49EE901NLGI | 功能描述:IC PLL CLK GEN 200MHZ 32VFQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:VersaClock™ III 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDT5V49EE901NLGI8 | 功能描述:IC PLL CLK GEN 200MHZ 32VFQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:VersaClock™ III 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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