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参数资料
| 型号： | IDT7006 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 高速16K的× 8双端口静态RAM |
| 文件页数： | 15/20页 |
| 文件大小： | 270K |
| 代理商： | IDT7006 |
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.07
15
WAVEFORM OF INTERRUPT TIMING
(1)
TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG
(1,4)
Left Port
R/
W
L
CE
L
OE
L
A
13L
-A
0L
L
L
X
X
X
X
X
X
X
X
L
L
Right Port
OE
R
INT
L
X
X
L
(3)
H
(2)
R/
W
R
X
X
L
X
CE
R
X
L
L
X
A
13R
-A
0R
INT
X
3FFF
3FFE
X
R
L
(2)
H
(3)
X
X
Function
3FFF
X
X
3FFE
X
L
X
X
Set Right
INT
R
Flag
Reset Right
INT
R
Flag
Set Left
INT
L
Flag
Reset Left
INT
L
Flag
NOTES:
1. Assumes
BUSY
L
=
BUSY
R
= V
IH
.
2. If
BUSY
L
= V
IL
, then no change.
3. If
BUSY
R
= V
IL
, then no change.
4.
INT
R and
INT
L
must be initialized at power-up.
2739 tbl 17
2739 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/
W
"A"
t
AS
t
WC
t
WR
(3)
(4)
t
INS(3)
INT
"B"
(2)
2739 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR(3)
INT
"B"
(2)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
4. Timing depends on which enable signal (
CE
or R/
W
) is de-asserted first.
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相关代理商/技术参数 |
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| IDT700620J | 制造商:未知厂家 制造商全称:未知厂家 功能描述:IC-SM-DUAL PORT SRAM |
| IDT7006L | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM |
| IDT7006L15F | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM |
| IDT7006L15FB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM |
| IDT7006L15G | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM |
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