参数资料
型号: IDT7008L25G
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/19页
文件大小: 0K
描述: IC SRAM 512KBIT 25NS 84PGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 512K (64K x 8)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 84-BPGA
供应商设备封装: 84-PGA(27.94x27.94)
包装: 托盘
其它名称: 7008L25G
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (1,3) (M/ S = V IH )
ADDR "A"
and "B"
CE "A"
CE "B"
t APS
(2)
ADDRESSES MATCH
t BAC
t BDC
BUSY "B"
3198 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (1) (M/ S = V IH )
ADDR "A"
ADDR "B"
ADDRESS "N"
t APS (2)
MATCHING ADDRESS "N"
BUSY "B"
t BAA
t BDA
3198 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (1)
7008X15
Com'l Only
7008X20
Com'l
& Ind
7008X25
Com'l &
Military
7008X35
Com'l &
Military
7008X55
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
15
15
0
0
____
____
____
____
20
20
0
0
____
____
____
____
20
20
0
0
____
____
____
____
25
25
0
0
____
____
____
____
40
40
ns
ns
ns
ns
3198 tbl 15
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
14
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