参数资料
型号: IDT70121S35J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 4/15页
文件大小: 0K
描述: IC SRAM 18KBIT 35NS 52PLCC
标准包装: 400
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 18K(2K x 9)
速度: 35ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 带卷 (TR)
其它名称: 70121S35J8
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1,4) (V CC = 5V ± 10%)
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
I CC
Dynamic Operating Current
CE = V IL , Outputs Disabled
COM'L
S
135
260
135
250
mA
(Both Ports Active)
L
135
220
135
210
f = f MAX (2)
IND
S
L
___
___
___
___
135
135
275
250
I SB1
Standby Current
CE "A" = CE "B" = V IH
COM'L
S
30
65
30
65
mA
(Both Ports - TTL Level Inputs)
L
30
45
30
45
f = f MAX
(2)
IND
S
___
___
30
80
L
___
___
30
65
I SB2
Standby Current
CE "A" = V IL and CE "B" = V IH (5)
COM'L
S
80
175
80
165
mA
(One Port - TTL Level Inputs)
Active Port Outputs Disabled,
f=f MAX (2)
IND
L
S
L
80
___
___
145
___
___
80
80
80
135
190
165
I SB3
Full Standby Current (Both Ports
- CMOS Level Inputs)
CE "A" and CE "B" > V CC - 0.2V
V IN > V CC - 0.2V or
VIN < 0.2V, f = 0 (3)
COM'L
IND
S
L
S
1.0
0.2
___
15
5
___
1.0
0.2
1.0
15
5
15
mA
L
___
___
0.2
5
I SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE "A" < 0.2V and
CE "B" > V CC - 0.2V (5)
COM'L
S
L
70
70
170
140
70
70
160
130
mA
V IN > V CC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = f MAX (2)
IND
S
L
___
___
___
___
70
70
185
160
2654 tbl 06a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
I CC
Dynamic Operating Current
CE = V IL , Outputs Disabled
COM'L
S
135
245
135
240
mA
(Both Ports Active)
L
135
205
135
200
f = f MAX
(2)
IND
S
L
___
___
___
___
___
___
___
___
I SB1
Standby Current
CE "A" = CE "B" = V IH
COM'L
S
30
65
30
65
mA
(Both Ports - TTL Level Inputs)
L
30
45
30
45
f = f MAX
(2)
IND
S
L
___
___
___
___
___
___
___
___
I SB2
Standby Current
CE "A" = V IL and CE "B" = V IH (5)
COM'L
S
80
160
80
155
mA
(One Port - TTL Level Inputs)
Active Port Outputs Disabled,
f=f MAX (2)
IND
L
S
L
80
___
___
130
___
___
80
___
___
125
___
___
I SB3
Full Standby Current
(Both Ports - CMOS Level
Inputs)
CE "A" and CE "B" > V CC - 0.2V
V IN > V CC - 0.2V or
V IN < 0.2V, f = 0 (3)
COM'L
IND
S
L
S
1.0
0.2
___
15
5
___
1.0
0.2
___
15
5
___
mA
L
___
___
___
___
I SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE "A" < 0.2V and
CE "B" > V CC - 0.2V (5)
COM'L
S
L
70
70
155
125
70
70
150
120
mA
V IN > V CC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = f MAX (2)
IND
S
L
___
___
___
___
___
___
___
___
NOTES:
2654 tbl 06b
1. 'X' in part numbers indicates power rating (S or L).
2. At f = f MAX , address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC , and using “AC TEST CONDITIONS” of
input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, T A =+25°C for Typ, and is not production tested.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
6.42
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