参数资料
型号: IDT70121S35J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/15页
文件大小: 0K
描述: IC SRAM 18KBIT 35NS 52PLCC
标准包装: 400
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 18K(2K x 9)
速度: 35ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 带卷 (TR)
其它名称: 70121S35J8
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (3)
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t RC
t AA
t ACE
t AOE
t OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
25
____
____
____
0
____
25
25
12
____
35
____
____
____
0
____
35
35
25
____
ns
ns
ns
ns
ns
t LZ
Output Low-Z Time
(1,2)
0
____
0
____
ns
t HZ
Output High-Z Time
(1,2)
____
10
____
15
ns
t PU
Chip Enable to Power Up Time
(2)
0
____
0
____
ns
t PD
Chip Disable to Power Down Time
(2)
____
50
____
50
ns
2654 tbl 09a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t RC
t AA
t ACE
t AOE
t OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
45
____
____
____
0
____
45
45
30
____
55
____
____
____
0
____
55
55
35
____
ns
ns
ns
ns
ns
t LZ
Output Low-Z Time
(1,2)
0
____
0
____
ns
t HZ
t PU
Output High-Z Time (1,2)
Chip Enable to Power Up Time (2)
____
0
20
____
____
0
30
____
ns
ns
t PD
Chip Disable to Power Down Time
(2)
____
50
____
50
ns
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
6.42
2654 tbl 09b
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