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| 型号： | IDT70261L20PFI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 256KBIT 20NS 100TQFP |
| 标准包装： | 45 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 256K（16K x 16） |
| 速度： | 20ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 70261L20PFI |
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Truth Table IV —
Address BUSY Arbitration
Industrial and Commercial Temperature Ranges
Inputs
Outputs
CE L
X
H
X
L
CE R
X
X
H
L
A OL -A 13L
A OR -A 13R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
(2)
BUSY R (1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit (3)
NOTES:
3039 tbl 17
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70261 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY R outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Le ft Port Writes "0" to Semaphore
Rig ht Port Writes "0" to Semaphore
Le ft Port Writes "1" to Semaphore
Le ft Port Writes "0" to Semaphore
Rig ht Port Writes "1" to Semaphore
Le ft Port Writes "1" to Semaphore
Rig ht Port Writes "0" to Semaphore
Rig ht Port Writes "1" to Semaphore
Le ft Port Writes "0" to Semaphore
Le ft Port Writes "1" to Semaphore
NOTES:
D0 - D15 Left
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 15 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
3039 tbl 18
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70261.
2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O 0 -I/O 15 ). These eight semaphores are addressed by A 0 - A 2 .
3. CE = V IH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT70261 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT70261 has an automatic power down feature
controlled by CE . The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
( CE = V IH ). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
( INT L ) is asserted when the right port writes to memory location 3FFE
(HEX), where a write is defined as CE R = R/ W R = V IL per Truth Table
III. The left port clears the interrupt through access of address location
3FFE when CE L = OE L = V IL , R/ W is a "don't care". Likewise, the right
port interrupt flag ( INT R ) is asserted when the left port writes to memory
location 3FFF (HEX) and to clear the interrupt flag ( INT R ), the right port
must read the memory location 3FFF. The message (16 bits) at 3FFE or
3FFF is user-defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and 3FFF are not
used as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
15
6.42
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| IDT70261L25PFI | 制造商:IDT 功能描述:SRAM Chip Async Dual 5V 256K-Bit 16K x 16 25ns 100-Pin TQFP Tray |
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