参数资料
型号: IDT7026L20J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/18页
文件大小: 0K
描述: IC SRAM 256KBIT 20NS 84PLCC
标准包装: 200
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 256K(16K x 16)
速度: 20ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC(29.21x29.21)
包装: 带卷 (TR)
其它名称: 7026L20J8
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (6,7)
7026X15
Com'l Only
7026X20
Com'l, Ind
& Military
7026X25
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S =V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Acce ss Time from Chip Enable Low
BUSY Acce ss Time from Chip Enable High
____
____
____
____
15
15
15
15
____
____
____
____
20
20
20
17
____
____
____
____
20
20
20
17
ns
ns
ns
ns
Write Hold After BUSY
t APS
t BDD
t WH
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
(5)
(2)
5
____
12
____
18
____
5
____
15
____
30
____
5
____
17
____
30
____
ns
ns
ns
BUSY TIMING (M/ S =V IL )
t WB
t WH
BUSY Input to Write (4)
Write Hold After BUSY (5)
0
12
____
____
0
15
____
____
0
17
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
30
____
45
____
50
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
30
____
35
ns
2939 tbl 14a
7026X35
Com'l, Ind
& Military
7026X55
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S =V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Acce ss Time from Chip Enable Low
BUSY Acce ss Time from Chip Enable High
____
____
____
____
20
20
20
20
____
____
____
____
45
40
40
35
ns
ns
ns
ns
BUSY Disable to Valid Data
Write Hold After BUSY
t APS
t BDD
t WH
Arbitration Priority Set-up Time
(3)
(5)
(2)
5
____
25
____
35
____
5
____
25
____
40
____
ns
ns
ns
BUSY TIMING (M/ S =V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
25
____
____
0
25
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
60
____
80
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
45
____
65
ns
NOTES:
2939 tbl 14b
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V IH )".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual), or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
12
6.42
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