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| 型号： | IDT7027S55PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 512KBIT 55NS 100TQFP |
| 标准包装： | 6 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 512K (32K x 16) |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 7027S55PF |
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of busy logic is not
desirable, the BUSY logic can be disabled by placing the part in slave mode
with the M/ S pin. Once in slave mode the BUSY pin operates solely as a
write inhibit input pin. Normal operation can be programmed by tying the
BUSY pins HIGH. If desired, unintended write operations can be pre-
vented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7027 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Industrial and Commercial Temperature Ranges
pulse can be initiated with either the R/ W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT7027 is a fast Dual-Port 32K x 16 CMOS Static RAM with an
additional 8 address locations dedicated to binary semaphore flags. These
flags allow either processor on the left or right side of the Dual-Port SRAM
to claim a privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore can be used
by one processor to inhibit the other from accessing a portion of the Dual-
Port SRAM or any other shared resource.
The Dual-Port SRAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
have an automatic power-down feature controlled by CE the Dual-Port
A 15
MASTER CE 0
Dual Port RAM
BUSY L BUSY R
SLAVE CE 0
Dual Port RAM
BUSY L BUSY R
SRAM enable, and SEM , the semaphore enable. The CE and SEM pins
control on-chip power down circuitry that permits the respective port to go
into standby mode when not selected. This is the condition which is shown
in Truth Table II where CE and SEM = V IH .
Systems which can best use the IDT7027 contain multiple processors
or controllers and are typically very high-speed systems which are
MASTER
Dual Port RAM
CE 1
SLAVE
Dual Port RAM
CE 1
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7027's hardware
BUSY L
BUSY L
BUSY R
BUSY L
BUSY R
BUSY R
semaphores, which provide a lockout mechanism without requiring
.
3199 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7027 RAMs.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7027 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master, use
the BUSY signal as a write inhibit signal. Thus on the IDT7027 RAM the
BUSY pin is an output if the part is used as a Master (M/ S pin = V IH ), and
the BUSY pin is an input if the part used as a Slave (M/ S pin = V IL ) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7027 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port SRAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to
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| IDT7027S55PF8 | 功能描述:IC SRAM 512KBIT 55NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT7028L15PF | 功能描述:IC SRAM 1MBIT 15NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,500 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（单线） 电源电压:1.8 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-MSOP 包装:带卷 (TR) |
| IDT7028L15PF8 | 功能描述:IC SRAM 1MBIT 15NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT7028L15PFG | 功能描述:IC SRAM 1MBIT 15NS 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 125°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) 其它名称:CAV24C32WE-GT3OSTR |
| IDT7028L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 1MBIT 15NS 100TQFP |
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