参数资料
型号: IDT7037L20PFI
厂商: IDT, Integrated Device Technology Inc
文件页数: 7/17页
文件大小: 0K
描述: IC SRAM 576KBIT 20NS 100TQFP
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 576K(32K x 18)
速度: 20ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 7037L20PFI
IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (5)
7037L15
Com'l Only
7037L20
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t RC
t AA
Read Cycle Time
Address Access Time
15
____
____
15
20
____
____
20
ns
ns
t ACE
t ABE
Chip Enable Access Time
Byte Enable Access Time
(4)
(4)
____
____
15
15
____
____
20
20
ns
ns
t AOE
t OH
Output Enable Access Time
Output Hold from Address Change
____
3
10
____
____
3
12
____
ns
ns
t LZ
Output Low-Z Time
(1,2)
3
____
3
____
ns
t HZ
Output High-Z Time
(1,2)
____
10
____
10
ns
t PU
Chip Enable to Power Up Time
(2)
0
____
0
____
ns
t PD
Chip Disable to Power Down Time
(2)
____
15
____
20
ns
t SOP
t SAA
Semaphore Flag Update Pulse ( OE or SEM )
Semaphore Address Access Time
10
____
____
15
10
____
____
20
ns
ns
4838 tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage (5)
7037L15
Com'l Only
7037L20
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
t EW
t AW
Write Cycle Time
Chip Enable to End-of-Write (3)
Address Valid to End-of-Write
15
12
12
____
____
____
20
15
15
____
____
____
ns
ns
ns
t AS
Address Set-up Time
(3)
0
____
0
____
ns
t WP
t WR
t DW
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
12
0
10
____
____
____
15
0
15
____
____
____
ns
ns
ns
t HZ
Output High-Z Time
(1,2)
____
10
____
10
ns
t DH
Data Hold Time
(4)
0
____
0
____
ns
Write Enable to Output in High-Z
t WZ
(1,2)
____
10
____
10
ns
t OW
t SWRD
t SPS
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
(1,2,4)
0
5
5
____
____
____
0
5
5
____
____
____
ns
ns
ns
NOTES:
4838 tbl 13
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . Either condition must be valid for the entire t EW time.
4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and t OW values will vary over voltage
and temperature, the actual t DH will always be smaller than the actual t OW .
5. Industrial Temperature: for specific speeds, packages and powers contact your sales office.
7
6.42
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