参数资料
型号: IDT7054L20G
厂商: IDT, Integrated Device Technology Inc
文件页数: 9/11页
文件大小: 0K
描述: IC SRAM 32KBIT 20NS 108PGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 四端口,异步
存储容量: 32K (4K x 8)
速度: 20ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 108-BSPGA
供应商设备封装: 108-PGA(30.48x30.48)
包装: 托盘
其它名称: 7054L20G
IDT7054S/L
High-Speed 4K x 8 FourPort? Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (5,8)
t WC
ADDRESS
t AS
OE
(6)
CE
t AW
t WR
(3)
R/ W
t WP (2)
t HZ
(7)
DATA OUT
t LZ
(4)
t WZ (7)
t OW
(4)
t HZ
(7)
t DW
t DH
DATA IN
3241 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,5)
t WC
ADDRESS
t AW
CE
t AS
t EW
(6)
(2)
t WR
(3)
R/ W
t DW
t DH
DATA IN
3241 drw 08
NOTES:
1. R/ W or CE = V IH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a CE = V IL and a R/ W = V IL .
3. t WR is measured from the earlier of CE or R/ W = V IH to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/ W .
7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production tested.
8. If OE = V IL during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be placed
on the bus for the required t DW . If OE = V IH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t WP .
9
6.42
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