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参数资料
| 型号： | IDT70P258L55BYI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 13/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 55NS 100BGA |
| 标准包装： | 3,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K（8K x 16） |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-VFBGA |
| 供应商设备封装： | 100-CABGA（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70P258L55BYI8 |
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70P258/248
Ind'l Only
Symbol
Parameter
Min.
Max.
Unit
BUSY TIMING (M/ S = V DD )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
____
____
____
____
45
45
45
45
ns
ns
ns
ns
t APS
t BDD
t WH
Arbitration Priority Set-up Time
BUSY Disable to Valid Data (3)
Write Hold After BUSY (5)
(2)
5
____
35
____
40
____
ns
ns
ns
BUSY TIMING (M/ S = V SS )
t WB
t WH
BUSY Input to Write (4)
Write Hold After BUSY (5)
0
35
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
t DDD
Write Pulse to Data Delay (1)
Write Data Valid to Read Data Delay (1)
____
____
80
65
ns
ns
NOTES:
5675 tbl 13
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/ S = V DD )" or "Timing Waveform of Write
With Port-To-Port Delay (M/ S = V SS )".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0ns, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
13
6.42
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