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参数资料
| 型号： | IDT70P258L55BYI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 16/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 55NS 100BGA |
| 标准包装： | 3,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K（8K x 16） |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-VFBGA |
| 供应商设备封装： | 100-CABGA（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70P258L55BYI8 |
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Waveform of Interrupt Timing (1)
t WC
Industrial Temperature Range
ADDR "A"
CE "A"
R/ W "A"
INT "B"
t AS (3)
t INS
(3)
(2)
INTERRUPT SET ADDRESS
t WR (4)
t RC
5675 drw 14
,
ADDR "B"
CE "B"
OE "B"
INT "B"
t AS (3)
t INR (3)
INTERRUPT CLEAR ADDRESS
(2)
,
5675 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/ W ) is de-asserted first.
16
6.42
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