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参数资料
| 型号： | IDT70P258L55BYI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 15/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 55NS 100BGA |
| 标准包装： | 3,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K（8K x 16） |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-VFBGA |
| 供应商设备封装： | 100-CABGA（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70P258L55BYI8 |
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Waveform of BUSY Arbitration Controlled by CE Timing (1) (M/ S = V IH )
ADDR "A"
and "B"
CE "A"
CE "B"
BUSY "B"
t APS (2)
t BAC
ADDRESSES MATCH
t BDC
,
5675 drw 12
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (1) (M/ S = V IH )
ADDR "A"
ADDR "B"
t APS
(2)
ADDRESS "N"
MATCHING ADDRESS "N"
BUSY "B"
t BAA
t BDA
,
5675 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70P258/248
Ind'l Only
Symbol
Parameter
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
45
45
ns
ns
ns
ns
5675 tbl 14
15
6.42
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