参数资料
型号: IDT70T3339S133BC
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/27页
文件大小: 0K
描述: IC SRAM 9MBIT 133MHZ 256BGA
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 9M(512K x 18)
速度: 133MHz
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 70T3339S133BC
HIGH-SPEED 2.5V
512/256/128K X 18
SYNCHRONOUS
IDT70T3339/19/99S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
True Dual-Port memory cells which allow simultaneous
Features:
access of the same memory location
– 1.5ns setup to clock and 0.5ns hold on all control, data,
and address inputs @ 200MHz
– Self-timed write allows fast cycle time
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– Data input, address, byte enable and control registers
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
UB L
LB L
UB R
LB R
FT /PIPE L
1/0
0a 1a
a
0b 1b
b
1b 0b
b
1a 0a
a
1/0
FT /PIPE R
R/ W L
R/ W R
CE 0L
CE 1L
1
0
B B
W W
B B
W W
1
0
CE 0R
CE 1R
0 1
1 0
OE L
1/0
1b 0b 1a 0a
L L
Dout0-8_L
Dout9-17_L
R R
Dout0-8_R
Dout9-17_R
0a 1a 0b
1/0
OE R
,
FT /PIPE L
0/1
ab
512/256/128K x 18
1b
ba
0/1
FT /PIPE R
MEMORY
ARRAY
CLK L
A 18L (1)
I/O 0L - I/O 17L
Din_L
Din_R
I/O 0R - I/O 17R
A 18R (1)
CLK R
,
A 0L
REPEAT L
ADS L
CNTEN L
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A 0R
REPEAT R
ADS R
CNTEN R
TDI
TCK
CE 0 L
CE1L
R/ W L
INTERRUPT
COLLISION
DETECTION
LOGIC
R/ W R
CE 0 R
CE1R
TDO
JTAG
TMS
TRST
COL L
INT L
COL R
INT R
ZZ L
(2)
ZZ
CONTROL
ZZ R
(2)
5652 drw 01
LOGIC
NOTES:
1. Address A 18 is a NC for the IDT70T3319. Also, Addresses A 18 and A 17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/ FT x and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
?2010 Integrated Device Technology, Inc.
APRIL 2010
DSC-5652/7
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