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参数资料
| 型号： | IDT70T3719MS166BBG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | DRAM |
| 英文描述： | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 256K X 72 DUAL-PORT SRAM, 12 ns, PBGA324 |
| 封装： | 19 X 19 MM, 1.40 MM HEIGHT, 1.76 MM PITCH, GREEN, BGA-324 |
| 文件页数： | 10/25页 |
| 文件大小： | 316K |
| 代理商： | IDT70T3719MS166BBG |
6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
AC Elec tric al Charac teristic s Over the Operating Temperature Range
(Read and Write Cyc le T iming)
(2,3)
(V
DD
= 2.5V ± 100mV , T
A
= 0°C to +70°C)
Advanced
10
NOTES:
1. The Pipelined output parameters (t
CYC2
, t
CD2
) apply to either or both left and right ports when
FT
/PIPE
X
= V
DD
(2.5V). Flow-through parameters (t
CYC1
, t
CD1
)
apply when
FT
/PIPE = V
ss
(0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (
OE
),
FT
/PIPE and OPT.
FT
/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of V
DDQ
(3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4. Guaranteed by design (not production tested).
70T3719/99M
S166
Com'l
Only
70T3719/99M
S133
Com'l
& Ind
Symbol
Parameter
Mn.
Max.
Min.
Max.
Unit
t
CYC1
Clock Cycle Time (Flow-Through)
(1)
20
____
25
____
ns
t
CYC2
Clock Cycle Time (Pipelined)
(1)
6
____
7.5
____
ns
t
CH1
Clock High Time (Flow-Through)
(1)
8
____
10
____
ns
t
CL1
Clock LowTime (Flow-Through)
(1)
8
____
10
____
ns
t
CH2
Clock High Time (Pipelined)
(2)
2.4
____
3
____
ns
t
CL2
Clock LowTime (Pipelined)
(1)
2.4
____
3
____
ns
t
SA
Address Setup Time
1.7
____
1.8
____
ns
t
HA
Address Hold Time
0.5
____
0.5
____
ns
t
SC
Chip Enable Setup Time
1.7
____
1.8
____
ns
t
HC
Chip Enable Hold Time
0.5
____
0.5
____
ns
t
SB
Byte Enable Setup Time
1.7
____
1.8
____
ns
t
HB
Byte Enable Hold Time
0.5
____
0.5
____
ns
t
SW
R/W Setup Time
1.7
____
1.8
____
ns
t
HW
R/W Hold Time
0.5
____
0.5
____
ns
t
SD
Input Data Setup Time
1.7
____
1.8
____
ns
t
HD
Input Data Hold Time
0.5
____
0.5
____
ns
t
SAD
ADS
Setup Time
1.7
____
1.8
____
ns
t
HAD
ADS
Hold Time
0.5
____
0.5
____
ns
t
SCN
CNTEN
Setup Time
1.7
____
1.8
____
ns
t
HCN
CNTEN
Hold Time
0.5
____
0.5
____
ns
t
SRPT
REPEAT
Setup Time
1.7
____
1.8
____
ns
t
HRPT
REPEAT
Hold Time
0.5
____
0.5
____
ns
t
OE
Output Enable to Data Valid
____
4.4
____
4.6
ns
t
OLZ
(4)
Output Enable to Output Low-Z
1
____
1
____
ns
t
OHZ
(4)
Output Enable to Output High-Z
1
3.6
1
4.2
ns
t
CD1
Clock to Data Valid (Flow-Through)
(1)
____
12
____
15
ns
t
CD2
Clock to Data Valid (Pipelined)
(1)
____
3.6
____
4.2
ns
t
DC
Data Output Hold After Clock High
1
____
1
____
ns
t
CKHZ
(4)
Clock High to Output High-Z
1
3.6
1
4.2
ns
t
CKLZ
(4)
Clock High to Output Low-Z
1
____
1
____
ns
t
INS
Interrupt Flag Set Time
____
7
____
7
ns
t
INR
Interrupt Flag Reset Time
____
7
____
7
ns
t
COLS
Collision Flag Set Time
____
3.6
____
4.2
ns
t
COLR
Collision Flag Reset Time
____
3.6
____
4.2
ns
t
ZZSC
Sleep Mode Set Cycles
2
____
2
____
cycles
t
ZZRC
Sleep Mode Recovery Cycles
3
____
3
____
cycles
Port-to-Port Delay
t
CO
Clock-to-Clock Offset
5
____
6
____
ns
t
OFS
Clock-to-Clock Offset for Collision Detection
Please refer to collision Detection Timng Table
on Page 19.
5687 tbl 12
相关PDF资料 |
PDF描述 |
|---|---|
| IDT70T3719MS166BBGI | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70T3799M | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70T3799MS133BBG | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70T3799MS133BBGI | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70T3799MS166BBG | HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
相关代理商/技术参数 |
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