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| 型号： | IDT70T9169L9PF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | DRAM |
| 英文描述： | HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| 中文描述： | 16K X 9 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 5/16页 |
| 文件大小： | 199K |
| 代理商： | IDT70T9169L9PF |
6.42
IDT70T9169/59L
High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
Preliminary
*++0
%+123
*++0
+
4'56*
"
"
%
4
789:7$5;
<
"
Grade
Ambient
Temperature
(1)
GND
V
DD
Commercial
0
O
C to +70
O
C
0V
2.5V
+
100mV
Industrial
-40
O
C to +85
O
C
0V
2.5V
+
100mV
5654 tbl 04
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
2.4
2.5
2.6
V
V
SS
Ground
0
0
0
V
V
IH
Input High Voltage
1.7
____
V
DD
+0.3V
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.7
V
5654 tbl 05
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
(3)
Output Capacitance
V
OUT
= 3dV
10
pF
5654 tbl 07
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Termnal Voltage
with Respect to
GND
-0.5 to +3.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output Current
50
mA
5654 tbl 06
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
and
OE
= V
IL
; CE
1
and R/
W
= V
IH
.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
CNTRST
are independent of all other signals including
CE
0
and CE
1
.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
and CE
1
.
%&%'(()4++
"
External
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS
CNTEN
CNTRST
I/O
(3)
MODE
An
X
An
↑
L
(4)
X
H
D
I/O
(n)
External Address Used
X
An
An + 1
↑
H
L
(5)
H
D
I/O
(n+1)
Counter Enabled
—
Internal Address generation
X
An + 1
An + 1
↑
H
H
H
D
I/O
(n+1)
External Address Blocked
—
Counter disabled (An + 1 reused)
X
X
A
0
↑
X
X
L
(4)
D
I/O
(0)
Counter Reset to Address 0
5654 tbl 03
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
DD
+0.3V.
NOTES:
1. These parameters are determned by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from0V to 3V or from3V to 0V.
3. C
OUT
also references C
I/O
.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximumrating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+ 0.3V for more than 25% of the cycle time or 10ns
maximum and is limted to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
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