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参数资料
| 型号： | IDT70V5378S100BG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 25/29页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 576KBIT 100MHZ 272BGA |
| 标准包装： | 40 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 四端口，同步 |
| 存储容量： | 576K（32K x 18） |
| 速度： | 100MHz |
| 接口： | 并联 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 272-BBGA |
| 供应商设备封装： | 272-PBGA（27x27） |
| 包装： | 托盘 |
| 其它名称： | 70V5378S100BG |
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IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort? Static RAM
in increments of four: masking bits 2, 1, and 0 configures
that port to count in increments of eight, and so on. The
ability to set the increments by which the counters will
advance gives the user the ability to interleave memory
operations among the ports, minimizing the concerns that
a given address might be written by more than one port at
any given point in time (an operation that would have
indeterminate results).
JTAG Support
The IDT70V5388/78 provides a serial boundary
scan test access port . The JTAG tables starting on page
29 provide the specific details for the JTAG implementation
on this device.
The IDT70V5388/78 executes a JTAG test logic
reset upon power-up. This power-up reset will initialize the
TAP controller and MBIST controller. In most power
environments no further action is required. However, if the
Industrial and Commercial Temperature Ranges
while a "1" indicates that the memory array passed. The rest
of the MRR contains the total number of failed read cycles
in the entire MBIST sequence.
The IDT70V5388/78 MBIST function has been
supplemented with the ability for the user to force a failure
report from the device. This allows the user the flexibility of
validating the MBIST function itself, by verifying that the
device is able to report faults as well as passing results. The
two modes of operation, normal MBIST testing and forced
error reporting, are controlled via the JTAG TAP interface
using the instruction PROGRAM_MBIST_MODE_SELECT.
For further detail, please refer to the System Interface
Parameters table on page 28.
The MBIST function executes once the RUNBIST
instruction is input via the JTAG interface. The entire MBIST
test will be performed with a deterministic number of TCK
cycles depending on the TCK and CLKMBIST frequency.
This can be calculated by using the following formula:
user has any concern about the system’s voltage states
during power-up, then the user can use the optional TRST
input as part of a board’s power on reset sequence. The
TRST pin also provides an alternate means of resetting the
t CYC =
t CYC [CLKMBIST]
t CYC [TCK]
x m + SPC, where:
JTAG test logic when required, and is available for use by
external JTAG controllers as an asynchronous reset signal.
If the user does not plan to rely on the optional TRST pin, but
wants to use JTAG functionality, the TRST pin should either
be tied HIGH (preferred implementation) or left floating.
If JTAG operations are not desired, the user has a
number of options for disabling the JTAG functions. One
would be to simply tie TCK LOW, leaving all other JTAG pins
floating (alternatively, TDI and TMS could be tied HIGH).
Since the device executes a JTAG reset upon power-up:
with TCK tied LOW, no further clocking of the TAP will occur
and no JTAG operations will take place. Alternatively, the
user can opt to tie TRST LOW (either in lieu of or in addition
to tying TCK LOW) and the TAP will be locked in a reset
condition, blocking all JTAG operations.
Memory Built-In-Test Operations
Go-NoGo Testing
The IDT70V5388/78 is equipped with a self-test
function that can be run by the user as the result of a single
instruction, implemented via the JTAG TAP interface. If
multiple FourPort devices are used on the same board, all
can execute MBIST simultaneously, facilitating board
checkout.
The MBIST function executes a Go-NoGo test
within the device, which then captures pass-fail information
and failure count in a special register called the MBIST
Result Register (MRR). Upon completion of the test, the
MRR can be scanned out via the JTAG interface, using the
internal scan operation. Bit zero of the MRR (MRR[0]) is a
don't care. Bit one of the MRR (MRR[1])indicates the pass/
fail status: a "0" indicates some sort of failure was noted,
25
6.42
t CYC is the total number of TCK cycles required to run
MBIST.
SPC is the synchronization padding cycles (typically 4-6
cycles, to accommodate state machine overhead, turn-
around cycles, etc.)
m is a constant that represents the number of read and write
operations required to run the internal MBIST algorithms
(14,811,136) for both IDT70V5388 and IDT70V5378.
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| IDT70V5378S100BG8 | 功能描述:IC SRAM 576KBIT 100MHZ 272BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70V5378S133BC | 功能描述:IC SRAM 576KBIT 133MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70V5378S133BC8 | 功能描述:IC SRAM 576KBIT 133MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70V5378S133BG | 功能描述:IC SRAM 576KBIT 133MHZ 272BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70V5378S133BG8 | 功能描述:IC SRAM 576KBIT 133MHZ 272BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
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