参数资料
型号: IDT70V9279L6PRF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/19页
文件大小: 0K
描述: IC SRAM 512KBIT 6NS 128TQFP
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 512K (32K x 16)
速度: 6ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 128-LQFP
供应商设备封装: 128-TQFP(14x20)
包装: 带卷 (TR)
其它名称: 70V9279L6PRF8
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read ( OE = V IL ) (3)
t CYC1
CLK
CE 0
CE 1
t CH1
t SC t HC
t CL1
t SB
t HB
UB , LB
t SW t HW
R/ W
t SW t HW
(4)
ADDRESS
An
An +1
An + 2
An + 2
An + 3
An + 4
t SA
t HA
t SD t HD
DATA IN
Dn + 2
(2)
t CD1
t CD1
t CD1
t CD1
t CKHZ
t DC
t CKLZ
DATA OUT
Qn
t DC
Qn + 1
(1)
Qn + 3
(1)
READ
NOP
(5)
WRITE
READ
3743 drw 13
,
Timing Waveform of Flow-Through Read-to-Write-to-Read ( OE Controlled) (3)
t CYC1
CLK
CE 0
CE 1
t CH1
t SC t HC
t CL1
t SB
t HB
UB , LB
t SW t HW
R/ W
t SW t HW
ADDRESS
(4)
An
An +1
An + 2
An + 3
An + 4
An + 5
t SA
t HA
t SD t HD
DATA IN
(2)
t CD1
t DC
Dn + 2
Dn + 3
t OE
t CD1
t CD1
t OHZ
DATA OUT
Qn
(1)
(1)
t CKLZ
Qn + 4
t DC
OE
READ
WRITE
READ
3743 drw 14
,
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE 0 , UB , LB , and ADS = V IL ; CE 1 , CNTEN , and CNTRST = V IH .
4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
14
6.42
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