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参数资料
| 型号： | IDT7130LA35TFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 13/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 8KBIT 35NS 64STQFP |
| 标准包装： | 40 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 8K (1K x 8) |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 托盘 |
| 其它名称： | 7130LA35TFG 800-1440 |
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/ W Controlled Timing) (1,5,8)
t WC
ADDRESS
t HZ (7)
OE
t AW
CE
t AS (6)
t WP (2)
t WR (3)
t HZ (7)
R/ W
t WZ (7)
t OW
DATA OUT
(4)
t DW
t DH
(4)
DATA IN
2689 drw 10
Timing Waveform of Write Cycle No. 2, ( CE Controlled Timing) (1,5)
t WC
ADDRESS
t AW
CE
R/ W
t AS (6)
t EW (2)
t DW
t WR (3)
t DH
DATA IN
2689 drw 11
NOTES:
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of CE = V IL and R/ W = V IL.
3. t WR is measured from the earlier of CE or R/ W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the HIGH impedance state.
6. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
7. This parameter is determined by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be placed on the
bus for the required t DW . If OE is HIGH during a R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .
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