参数资料
型号: IDT7130SA55P
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/21页
文件大小: 0K
描述: IC SRAM 8KBIT 55NS 48DIP
标准包装: 7
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 8K (1K x 8)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 48-DIP(0.600",15.24mm)
供应商设备封装: 48-PDIP
包装: 管件
其它名称: 7130SA55P
IDT7130SA55P-ND
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side (1)
t RC
ADDRESS
t OH
t AA
t OH
DATA OUT
BUSY OUT
PREVIOUS DATA VALID
t BDDH (2,3)
DATA VALID
2689 drw 08
NOTES:
1. R/ W = V IH , CE = V IL , and is OE = V IL . Address is valid prior to the coincidental with CE transition LOW.
2. t BDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA , and t BDD .
Timing Waveform of Read Cycle No. 2, Either Side (3)
t ACE
CE
OE
DATA OUT
t AOE (4)
t LZ (1)
t HZ (2)
VALID DATA
t HZ (2)
I CC
CURRENT
t PU
t LZ
50%
(1)
t PD (4)
50%
I SS
2689 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CE .
2. Timing depends on which signal is deaserted first, OE or CE .
3. R/ W = V IH and OE = V IL , and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA , and t BDD .
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