参数资料
型号: IDT71321LA25PFI8
厂商: IDT, Integrated Device Technology Inc
文件页数: 9/17页
文件大小: 0K
描述: IC SRAM 16KBIT 25NS 64TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 16K (2K x 8)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 71321LA25PFI8
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temeprature and Supply Voltage Range (4)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
Write Pulse Width
t WC
t EW
t AW
t AS
t WP
t WR
t DW
Write Cycle Time (2)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
(3)
Write Recovery Time
Data Valid to End-of-Write
20
15
15
0
15
0
10
____
____
____
____
____
____
____
25
20
20
0
15
0
12
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1)
____
10
____
10
ns
t DH
t WZ
t OW
Data Hold Time
Write Enable to Output in High-Z (1)
Output Active from End-of-Write (1)
0
____
0
____
10
____
0
____
0
____
10
____
ns
ns
ns
2691 tbl 09a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
t EW
t AW
t AS
t WP
t WR
t DW
Write Cycle Time (2)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width (3)
Write Recovery Time
Data Valid to End-of-Write
35
30
30
0
25
0
15
____
____
____
____
____
____
____
55
40
40
0
30
0
20
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1)
____
15
____
25
ns
Write Enable to Output in High-Z
t DH
t WZ
Data Hold Time
(1)
0
____
____
15
0
____
____
30
ns
ns
t OW
Output Active from End-of-Write
(1)
0
____
0
____
ns
NOTES:
2691 tbl 09b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, t WC = t BAA + t WP , since R/ W = V IL must occur after t BAA .
3. If OE is LOW during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be
placed on the bus for the required t DW . If OE is HIGH during a R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t WP .
4. 'X' in part numbers indicates power rating (SA or LA).
9
6.42
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