- 您现在的位置：买卖IC网 > PDF目录4116 > IDT7133LA70J8 (IDT, Integrated Device Technology Inc)IC SRAM 32KBIT 70NS 68PLCC PDF资料下载
参数资料
| 型号： | IDT7133LA70J8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/17页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 32KBIT 70NS 68PLCC |
| 标准包装： | 250 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 32K（2K x 16） |
| 速度： | 70ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC（24x24） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7133LA70J8 |
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage (6)
7133X20
7143X20
Com'l Only
7133X25
7143X25
Com'l & Ind
7133X35
7143X35
Com'l
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER 71V33)
t BAA
t BDA
t BAC
t BDC
t WDD
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay (1)
____
____
____
____
____
20
20
20
17
40
____
____
____
____
____
20
20
20
20
50
____
____
____
____
____
30
30
25
25
60
ns
ns
ns
ns
ns
t DDD
t BDD
Write Data Valid to Read Data Delay
BUSY Disable to Valid Data (2)
(1)
____
____
30
25
____
____
35
30
____
____
45
35
ns
ns
t APS
t WH
Arbitration Priority Set-up Time
Write Hold After BUSY (5)
(3)
5
20
____
____
5
20
____
____
5
25
____
____
ns
ns
BUSY INPUT TIMING (For SLAVE 71V43)
t WB
t WH
BUSY Input to Write (4)
Write Hold After BUSY (5)
0
20
____
____
0
20
____
____
0
25
____
____
ns
ns
t WDD
Write Pulse to Data Delay
(1)
____
40
____
50
____
60
ns
t DDD
Write Data Valid to Read Data Delay (1)
____
30
____
35
____
45
ns
2746 tbl 12a
7133X45
7143X45
Com'l Only
7133X55
7143X55
Com'l, Ind
& Military
7133X70/90
7143X70/90
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER 71V33)
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
____
____
____
____
40
40
30
25
____
____
____
____
40
40
35
30
____
____
____
____
45/45
45/45
35/35
30/30
ns
ns
ns
ns
t WDD
Write Pulse to Data Delay
(1)
____
80
____
80
____
90/90
ns
t DDD
Write Data Valid to Read Data Delay (1)
____
55
____
55
____
70/70
ns
t BDD
BUSY Disable to Valid Data
(2)
____
40
____
40
____
40/40
ns
t APS
Arbitration Priority Set-up Time (3)
5
____
5
____
5/5
____
ns
t WH
Write Hold After BUSY
(5)
30
____
30
____
30/30
____
ns
BUSY INPUT TIMING (For SLAVE 71V43)
t WB
BUSY Input to Write (4)
0
____
0
____
0/0
____
ns
t WH
Write Hold After BUSY
(5)
30
____
30
____
30/30
____
ns
t WDD
Write Pulse to Data Delay
(1)
____
80
____
80
____
90/90
ns
t DDD
Write Data Valid to Read Data Delay (1)
____
55
____
55
____
70/70
ns
2746 tbl 12b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy".
2. t BDD is calculated parameter and is greater of 0, t WDD - t WP (actual) or t DDD - t DW (actual).
3. To ensure that the earlier of the two ports wins.
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (SA or LA).
10
6.42
相关PDF资料 |
PDF描述 |
|---|---|
| 84982-9 | CONN FFC 9POS 1MM VERT SMD |
| IDT7134SA35J8 | IC SRAM 32KBIT 35NS 52PLCC |
| FMC35DRXN | CONN EDGECARD 70POS DIP .100 SLD |
| 3-1734592-7 | CONN FPC 37POS .5MM RT ANG SMD |
| IDT71342SA35J8 | IC SRAM 32KBIT 35NS 52PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT7133LA90G | 功能描述:IC SRAM 32KBIT 90NS 68PGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT7133LA90GB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 90NS 68PGA |
| IDT7133LA90J | 功能描述:IC SRAM 32KBIT 90NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT7133LA90J8 | 功能描述:IC SRAM 32KBIT 90NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT7133S55J | 制造商:Integrated Device Technology Inc 功能描述: |
发布紧急采购，3分钟左右您将得到回复。