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参数资料
| 型号： | IDT7133LA70J8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/17页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 32KBIT 70NS 68PLCC |
| 标准包装： | 250 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 32K（2K x 16） |
| 速度： | 70ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC（24x24） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7133LA70J8 |
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Description
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.
The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port
RAM or as a “MASTER” Dual-Port RAM together with the IDT7143
“SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
Both devices provide two independent ports with separate control,
Pin Configurations (1,2,3)
INDEX
Military, Industrial and Commercial Temperature Ranges
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature, controlled by CE , permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology. Low-power
(LA) versions offer battery backup data retention capability, with each port
typically consuming 200μW for a 2V battery.
The IDT7133/7143 devices have identical pinouts. Each is packed in
a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin TQFP.
Military grade product is manufactured in compliance with the latest revision
of MIL-PRF-38535 QML, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
9
8
7
6
5
4
3
2
68 67 66 65 64 63 62 61
I/O 9L
I/O 10L
I/O 11L
I/O 12L
I/O 13L
I/O 14L
I/O 15L
V CC (1)
GND (2)
I/O 0R
I/O 1R
I/O 2R
I/O 3R
I/O 4R
I/O 5R
I/O 6R
I/O 7R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
IDT7133/43
J68-1 / F68-1 (4)
68-Pin PLCC/Flatpack
Top View (5)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A 6L
A 5L
A 4L
A 3L
A 2L
A 1L
A 0L
BUSY L
CE L
CE R
BUSY R
A 0R
A 1R
A 2R
A 3R
A 4R
A 5R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2746 drw 02
Index
N/C
N/C
N/C
N/C
I/O 10L
I/O 11L
I/O 12L
I/O 13L
GND
1
2
3
4
5
6
7
8
9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
N/C
N/C
N/C
N/C
A 5L
A 4L
A 3L
A 2L
A 1L
I/O 14L
I/O 15L
V CC
GND
I/O 0R
I/O 1R
I/O 2R
V CC
10
11
12
13
14
15
16
17
IDT7133/43PF
PN100-1 (4)
100-Pin TQFP
Top View (5)
66
65
64
63
62
61
60
59
A 0L
N/C
BUSY L
GND
N/C
BUSY R
N/C
A 0R
NOTES:
1. Both V CC pins must be connected to the power supply to ensure reliable
operation.
2. Both GND pins must be connected to the ground supply to ensure reliable
I/O 3R
I/O 4R
I/O 5R
I/O 6R
N/C
18
19
20
21
22
58
57
56
55
54
A 1R
A 2R
A 3R
A 4R
N/C
operation.
3. J68-Package body is approximately 0.95 in x 0.95 in x 0.17 in.
F68-Package body is approximately 1.18 in x 1.18 in x 0.16 in.
PN100-Package body is approximately 14mm x 14mm x 1.4mm.
N/C
N/C
N/C
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C
N/C
N/C
2746 drw 03
,
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
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