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参数资料
| 型号： | IDT7133LA70J8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 15/17页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 32KBIT 70NS 68PLCC |
| 标准包装： | 250 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 32K（2K x 16） |
| 速度： | 70ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC（24x24） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7133LA70J8 |
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I – Non-Contention Read/Write Control (4)
LEFT OR RIGHT PORT (1)
R/ W LB
X
X
L
L
H
L
H
H
H
R/ W UB
X
X
L
H
L
H
L
H
H
CE
H
H
L
L
L
L
L
L
L
OE
X
X
X
L
L
H
H
L
H
I/O 0-7
Z
Z
DATA IN
DATA IN
DATA OUT
DATA IN
Z
DATA OUT
Z
I/O 8-15
Z
Z
DATA IN
DATA OUT
DATA IN
Z
DATA IN
DATA OUT
Z
Function
Port Disabled and in Power Down Mode, I SB2 , I SB4
CE R = CE L = V IH , Power Down Mode, I SB1 or I SB3
Data on Lower Byte and Upper Byte Written into Memory (2)
Data on Lower Byte Written into Memory (2) , Data in Memory Output on
Upper Byte (3)
Data in Memory Output on Lower Byte (3) , Data on Upper Byte Written into
Memory (2)
Data on Lower Byte Written into Memory (2)
Data on Upper Byte Written into Memory (2)
Data in Memory Output on Lower Byte and Upper Byte
High Impedance Outputs
NOTES:
1. A 0L - A 10L ≠ A 0R - A 10R
2. If BUSY = LOW, data is not written.
3. If BUSY = LOW, data may not be valid, see t WDD and t DDD timing.
4. "H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte
Truth Table II — Address BUSY
Arbitration
2746 tbl 13
Inputs
Outputs
CE L
X
H
X
L
CE R
X
X
H
L
A 0L -A 10L
A 0R -A 10R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
(2)
BUSY R (1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit (3)
NOTES:
2746 tbl 14
1. Pins BUSY L and BUSY R are both outputs on the IDT7133 (MASTER). Both are
inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits
writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. “H” if the inputs to the opposite port became stable after the
address and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R
= V IL will result BUSY L and BUSY R outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSY R outputs are driving LOW regardless of actual logic level on
the pin.
15
6.42
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