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| 型号： | IDT71T75602S150PFG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 18MBIT 150MHZ 100TQFP |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 18M（512K x 36） |
| 速度： | 150MHz |
| 接口： | 并联 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 71T75602S150PFG8 |
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT? SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Description (cont.)
The data bus will tri-state two cycles after the chip is deselected or a write
is initiated.
The IDT71T75602/802 have an on-chip burst counter. In the burst
mode, the IDT71T75602/802 can provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the LBO input pin. The LBO pin selects
between linear and interleaved burst sequence. The ADV/ LD signal is
Pin Definitions (1)
used to load a new external address (ADV/ LD = LOW) or increment
the internal burst counter (ADV/ LD = HIGH).
The IDT71T75602/802 SRAMs utilize a high-performance 2.5V
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
Symbol
A 0 -A 19
Pin Function
Address Inputs
I/O
I
Active
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/ LD low, CEN low, and true chip enables.
ADV/ LD
Advance / Load
I
N/A
ADV/ LD is a synchronous input that is used to load the internal registers with new address and control when it is
sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with the chip deselected,
any burst in progress is terminated. When ADV/ LD is sampled high then the internal burst counter is advanced
for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled high.
R/ W
Read / Write
I
N/A
R/ W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
CEN
Clock Enable
I
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
BW 1 - BW 4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(when R/ W and ADV/ LD are sampled low) the appropriate byte write signal ( BW 1 - BW 4 ) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is sampled
high. The appropriate byte(s) of data are written into the device two cycles later. BW 1 - BW 4 can all be tied low if
always doing write to the entire 36-bit word.
CE 1 , CE 2
Chip Enables
I
LOW
Synchronous active low chip enable. CE 1 and CE 2 are used with CE 2 to enable the IDT71T75602/802 ( CE 1 or CE 2
sampled high or CE 2 sampled low) and ADV/ LD low at the rising edge of clock, initiates a deselect cycle. The
ZBT TM has a two cycle de select, i.e., the data bus will tri-state two clo ck cycles after deselect is initiated.
CE 2
Chip Enable
I
HIGH
Synchronous active high chip enable. CE 2 is used with CE 1 and CE 2 to enable the chip. CE 2 has inverted polarity
but otherwise identical to CE 1 and CE 2 .
CLK
Clock
I
N/A
This is the clock input to the IDT71T75602/802. Except for OE , all timing references for the device are made with
respect to the rising edge of CLK.
I/O 0 -I/O 31
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered
I/O P1 -I/O P4
by the rising edge of CLK.
LBO
OE
Linear Burst Order
Output Enable
I
I
LOW
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the
Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
Asynchronous output enable. OE must be low to read data from the 71T75602/802. Whe n OE is high the I/O pins
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS
TDI
TCK
TDO
TRST
ZZ
V DD
V DDQ
V SS
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset
(Optional)
Sleep Mode
Power Supply
Power Supply
Ground
I
I
I
O
I
I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LOW
HIGH
N/A
N/A
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inp uts are captured on rising edge of TCK, while
test outputs are d riven from the falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs
automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left
floating. This pin has an internal pullup. Only available in BGA package.
Synchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its
lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown.
2.5V core power supply.
2.5V I/O Supply.
Ground.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
5313 tbl 02
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相关代理商/技术参数 |
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| IDT71T75602S150PFGI | 功能描述:IC SRAM 18MBIT 150MHZ 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT71T75602S150PFGI8 | 功能描述:IC SRAM 18MBIT 150MHZ 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT71T75602S150PFI | 功能描述:IC SRAM 18MBIT 150MHZ 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 05/Nov/2008 标准包装:84 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 ZBT 存储容量:4.5M（128K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:119-BGA 供应商设备封装:119-PBGA（14x22） 包装:托盘 其它名称:71V3557SA75BGI |
| IDT71T75602S150PFI8 | 功能描述:IC SRAM 18MBIT 150MHZ 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 05/Nov/2008 标准包装:84 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 ZBT 存储容量:4.5M（128K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:119-BGA 供应商设备封装:119-PBGA（14x22） 包装:托盘 其它名称:71V3557SA75BGI |
| IDT71T75602S166BG | 功能描述:IC SRAM 18MBIT 166MHZ 119BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
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