参数资料
型号: IDT71V30L25TFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/14页
文件大小: 0K
描述: IC SRAM 8KBIT 25NS 64TQFP
标准包装: 40
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 8K (1K x 8)
速度: 25ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 托盘
其它名称: 71V30L25TFG
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Timing Waveform of Write with BUSY (3)
t WP
R/ W 'A'
t WB
BUSY 'B'
Industrial and Commercial Temperature Ranges
t WH
(1)
NOTES:
1. t WH must be met for BUSY .
R/ W 'B'
(2)
3741 drw 11
,
2. BUSY is asserted on port 'B' blocking R/ W 'B' , until BUSY 'B' goes HIGH.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of BUSY Arbitration Controlled by CE Timing (1)
ADDR
'A' AND 'B'
CE 'B'
CE 'A'
t APS (2)
t BAC
ADDRESSES MATCH
t BDC
BUSY 'A'
3741 drw 12
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
Timing Waveform of BUSY Arbitration Controlled Address Match Timing (1)
t RC
OR t WC
ADDR 'A'
ADDR 'B'
t APS
(2)
ADDRESSES MATCH
t BAA
ADDRESSES DO NOT MATCH
t BDA
BUSY 'B'
3741 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
10
6.42
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