参数资料
型号: IDT71V30L25TFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/14页
文件大小: 0K
描述: IC SRAM 8KBIT 25NS 64TQFP
标准包装: 40
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 8K (1K x 8)
速度: 25ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 托盘
其它名称: 71V30L25TFG
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side (1)
t RC
ADDRESS
t OH
t AA
t OH
DATA OUT
BUSY OUT
PREVIOUS DATA VALID
t BDD (2,3)
DATA VALID
3741 drw 06
NOTES:
1. R/ W = V IH , CE = V IL , and is OE = V IL . Address is valid prior to the coincidental with CE transition LOW.
2. t BDD delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultaneous read operations BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA , and t BDD .
Timing Waveform of Read Cycle No. 2, Either Side (3)
t ACE
CE
t AOE
(4)
t HZ
(2)
OE
DATA OUT
t LZ
(1)
VALID DATA
t HZ
(2)
I CC
t PU
t LZ
(1)
t PD
(4)
CURRENT
50%
50%
I SS
3741 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE .
2. Timing depends on which signal is desserted first, OE or CE .
3. R/ W = V IH and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last t AOE , t ACE , and t BDD .
6.42
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