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参数资料
| 型号： | IDT71V546S100PFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 4MBIT 100MHZ 100TQFP |
| 标准包装： | 72 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 4.5M（128K x 36） |
| 速度： | 100MHz |
| 接口： | 并联 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 71V546S100PFG 800-2325 IDT71V546S100PFG-ND |
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT ? Feature, Burst Counter and Pipelined Outputs
Pin Definitions (1)
Commercial and Industrial Temperature Ranges
Symbol
A 0 - A 16
Pin Function
Address Inputs
I/O
I
Active
N/A
Description
Synchronous Address inputs. The address register is triggered by a
combination of the rising edge of CLK and ADV/ LD Low, CEN Low and true
chip enables.
ADV/ LD
Address/Load
I
N/A
ADV/ LD is a synchronous input that is used to load the internal registers with
new address and control when it is sampled low at the rising edge of clock with
the chip selected. When ADV/ LD is low with the chip deselected, any burst in
progress is terminated. When ADV/ LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/ LD is sampled high.
R/ W
Read/Write
I
N/A
R/ W signal is a synchronous input that identified whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place two clock cycles later.
CEN
Clock Enable
I
LOW
Synchrono us Clock Enable Input. When CEN is sampled high, all other
synchronous inputs, including clock are ignored and outputs remain unchanged.
The effect of CEN samp led high on the device outputs is as if the low to high
clock transition did not occur. For normal operation, CEN must be sampled low
at rising edge of clock.
BW 1 - BW 4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. Enable 9-bit byte has its own active low byte
write enable. On load write cycles (When R/ W and ADV/ LD are sampled low)
the appropriate byte write signal ( BW 1 - BW 4 ) must be valid. The byte write
signal must also be valid on each cycle of a burs t write. Byte Write signals are
ignored when R/ W is sampled high. The appropriate byte(s) of data are written
into the device two cycles later. BW 1 - BW 4 can all be tied low if always doing
write to the entire 36-bit word.
CE 1 , CE 2
Chip Enables
I
LOW
Synchronous active low chip enable. CE 1 and CE 2 are used with CE 2 to
enable the IDT71V546. ( CE 1 or CE 2 sampled high or CE 2 sampled low) and
ADV/ LD low at the rising edge of clock, initiates a deselect cycle. the ZBT ?
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after
deselect is initiated.
CE2
CLK
Chip Enable
Clock
I
I
HIGH
N/A
Synchronout active high chip enable. CE 2 is used with CE 1 and CE 2 to enable
the chip. CE 2 has inverted polarity but otherwise identical to CE 1 and CE 2 .
This is the clock input to the IDT71V546. Except for OE , all timing references for
the device are made with respect to the rising edge of CLK.
I/O 0 - I/O 31
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data
I/O P1 - I/O P4
output path are registered and triggered by the rising edge of CLK.
LBO
Linear Burst
Order
I
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is
selected. When LBO is low the Linear burst sequence is selected. LBO is a
static DC input.
OE
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71V546.
When OE is high the I/O pins are in a high-impedance state. OE does not need
to be actively controlled for read and write cycles. In normal operation, OE can
be tied low.
V DD
V SS
Power Supply
Ground
N/A
N/A
N/A
N/A
3.3V power supply input.
Ground pin.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
3821 tbl 02
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71V546S100PFG8 | 功能描述:IC SRAM 4MBIT 100MHZ 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| IDT71V546S100PFGI | 功能描述:IC SRAM 4MBIT 100MHZ 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,000 系列:MoBL® 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并联 电源电压:2.2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-VFBGA 供应商设备封装:48-VFBGA（6x8） 包装:带卷 (TR) |
| IDT71V546S100PFGI8 | 功能描述:IC SRAM 4MBIT 100MHZ 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,000 系列:MoBL® 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并联 电源电压:2.2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-VFBGA 供应商设备封装:48-VFBGA（6x8） 包装:带卷 (TR) |
| IDT71V546S100PFI | 功能描述:IC SRAM 4MBIT 100MHZ 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V546S100PFI8 | 功能描述:IC SRAM 4MBIT 100MHZ 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
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