- 您现在的位置：买卖IC网 > PDF目录296206 > IDT71V65802S150BGG (INTEGRATED DEVICE TECHNOLOGY INC) 512K X 18 ZBT SRAM, 3.8 ns, PBGA119 PDF资料下载
参数资料
| 型号： | IDT71V65802S150BGG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 3.8 ns, PBGA119 |
| 封装： | 14 X 22 MM, GREEN, PLASTIC, BGA-119 |
| 文件页数： | 1/26页 |
| 文件大小： | 970K |
| 代理商： | IDT71V65802S150BGG |
OCTOBER 2004
DSC-5303/05
1
2004 Integrated Device Technology, Inc.
Pin Description Summary
Description
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs. They are designed to eliminate dead
bus cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or Zero
Bus Turnaround.
Features
x
256K x 36, 512K x 18 memory configurations
x
Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
x
ZBTTM Feature - No dead cycles between write and read cycles
x
Internally synchronized output buffer enable eliminates the
need to control
OE
x
Single R/
W
W (READ/WRITE) control pin
x
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x
4-word burst capability (interleaved or linear)
x
Individual byte write (
BW
BW1 - BW
BW
BW4) control (May tie active)
x
Three chip enables for simple depth expansion
x
3.3V power supply (±5%)
x
2.5V I/O Supply (VDDQ)
x
Power down controlled by ZZ input
x
Packaged in a JEDEC standard 100-pin plastic thin quad and
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
A0-A18
Address Inputs
Input
Synchronous
CE1, CE2, CE2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance burst address / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
ZZ
Sleep Mode
Input
Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
Static
VSS
Ground
Supply
Static
5303 tbl 01
256K x 36, 512K x 18
3.3V Synchronous ZBT SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71V65602
IDT71V65802
Address and control signals are applied to the SRAM during one clock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
The IDT71V65602/5802 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeusedto
disabletheoutputsatanygiventime.
A Clock Enable (
CEN) pin allows operation of the IDT71V65602/5802
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored
when (
CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
There are three chip enable pins (
CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three are not
asserted when ADV/
LD is low, no new memory operation can be initiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.The
databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.
The IDT71V65602/5802 have an on-chip burst counter. In the burst
mode, the IDT71V65602/5802 can provide four cycles of data for a single
addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined
bythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence.TheADV/
LDsignalisusedtoloadanewexternaladdress(ADV/
LD= LOW) or increment the internal burst counter (ADV/LD= HIGH).
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-
pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA)
and a 165 fine pitch ball grid array (fBGA).
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT71V65903S85BQG | 512K X 18 ZBT SRAM, 8.5 ns, PBGA165 |
| 71V65703S75PF8 | 256K X 36 ZBT SRAM, 7.5 ns, PQFP100 |
| 71V65703S75BGG | 256K X 36 ZBT SRAM, 7.5 ns, PBGA119 |
| IDT71V65903S80B | 512K X 18 ZBT SRAM, 8 ns, PBGA119 |
| IDT7210L25PQF | 16-BIT, DSP-MULTIPLIER ACCUMULATOR/SUMMER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71V65802S150BGG8 | 功能描述:IC SRAM 9MBIT 150MHZ 119BGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V65802S150BQ | 功能描述:IC SRAM 9MBIT 150MHZ 165FBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V65802S150BQ8 | 功能描述:IC SRAM 9MBIT 150MHZ 165FBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V65802S150PF | 功能描述:IC SRAM 9MBIT 150MHZ 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V65802S150PF8 | 功能描述:IC SRAM 9MBIT 150MHZ 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
发布紧急采购，3分钟左右您将得到回复。