- 您现在的位置：买卖IC网 > PDF目录296206 > IDT71V65903S80B (INTEGRATED DEVICE TECHNOLOGY INC) 512K X 18 ZBT SRAM, 8 ns, PBGA119 PDF资料下载
参数资料
| 型号： | IDT71V65903S80B |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 8 ns, PBGA119 |
| 封装： | 14 X 22 MM, PLASTIC, MS-026AA, BGA-119 |
| 文件页数： | 1/26页 |
| 文件大小： | 972K |
| 代理商： | IDT71V65903S80B |
DECEMBER 2002
DSC-5298/03
1
2002 Integrated Device Technology, Inc.
Pin Description Summary
cycle, and on the next clock cycle the associated data cycle occurs, be it
read or write.
The IDT71V65703/5903 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (
CEN) pin allows operation of the IDT71V65703/5903
tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen
CENishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.
There are three chip enable pins (
CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
assertedwhenADV/
LDislow,nonewmemoryoperationcanbeinitiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
isinitiated.
The IDT71V65703/5903 have an on-chip burst counter. In the burst
mode, the IDT71V65703/5903 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/
LD signal is used to load a new
externaladdress(ADV/
LD=LOW)orincrementtheinternalburstcounter
(ADV/
LD = HIGH).
The IDT71V65703/5903 SRAMs utilize IDT’s latest high-performance
CMOSprocessandarepackagedinaJEDECStandard14mmx20mm100-
pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
Features
x
256K x 36, 512K x 18 memory configurations
x
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
x
ZBTTM Feature - No dead cycles between write and read
cycles
x
Internally synchronized output buffer enable eliminates the
need to control
OE
x
Single R/
W
W (READ/WRITE) control pin
x
4-word burst capability (Interleaved or linear)
x
Individual byte write (
BW
BW1 - BW
BW
BW4) control (May tie active)
x
Three chip enables for simple depth expansion
x
3.3V power supply (±5%)
x
3.3V (±5%) I/O Supply (VDDQ)
x
Power down controlled by ZZ input
x
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBTTM, or Zero Bus Turnaround.
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
A0-A18
Address Inputs
Input
Synchronous
CE1, CE2, CE2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance Burst Address/Load New Address
Input
Synchronous
LBO
Linear/Interleaved Burst Order
Input
Static
ZZ
Sleep Mode
Input
Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input/Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
Static
VSS
Ground
Supply
Static
5298 tbl 01
IDT71V65703
IDT71V65903
256K x 36, 512K x 18
3.3V Synchronous ZBT SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT7210L25PQF | 16-BIT, DSP-MULTIPLIER ACCUMULATOR/SUMMER, PQFP64 |
| IDT7281L25SOI | 512 X 9 OTHER FIFO, 25 ns, PDSO28 |
| 7200L20TDB | 256 X 9 OTHER FIFO, 20 ns, CDIP28 |
| IDT7281L25TPI | 512 X 9 OTHER FIFO, 25 ns, PDIP28 |
| IDT7284L20PAI | 4K X 9 BI-DIRECTIONAL FIFO, 20 ns, PDSO56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71V65903S80BG | 功能描述:IC SRAM 9MBIT 80NS 119BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT71V65903S80BG8 | 功能描述:IC SRAM 9MBIT 80NS 119BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT71V65903S80BGI | 功能描述:IC SRAM 9MBIT 80NS 119BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT71V65903S80BGI8 | 功能描述:IC SRAM 9MBIT 80NS 119BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT71V65903S80BQ | 功能描述:IC SRAM 9MBIT 80NS 165FBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
发布紧急采购，3分钟左右您将得到回复。