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参数资料
| 型号： | IDT71V65903S85PFI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/26页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 9MBIT 85NS 100TQFP |
| 标准包装： | 72 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 9M（512K x 18） |
| 速度： | 85ns |
| 接口： | 并联 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 71V65903S85PFI |
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT? SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Synchronous Truth Table (1)
CEN
R/ W
CE 1 , CE 2 (5)
ADV/ LD
BWx
ADDRESS
PREVIOUS CYCLE
CURRENT CYCLE
I/O
USED
(One cycle later)
L
L
L
L
H
X
L
L
X
L
L
H
Valid
X
Valid
External
External
Internal
X
X
LOAD WRITE /
LOAD WRITE
LOAD READ
BURST WRITE
D (7)
Q (7)
D (7)
BURST WRITE
(Advance burst counter) (2)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
Q (7)
BURST READ
(Advance burst counter) (2)
SUSPEND
L
L
H
X
X
X
H
X
X
L
H
X
X
X
X
X
X
X
X
DESELECT / NOOP
X
DESELECT or STOP (3)
NOOP
(4)
HIZ
HIZ
Previous Value
NOTES:
5298 tbl 08
1. L = V IL , H = V IH , X = Don’t Care.
2. When ADV/ LD signal is sampled high, the internal burst counter is incremented. The R/ W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/ W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either ( CE 1 , or CE 2 is sampled high or CE 2 is sampled low) and ADV/ LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE 1 = L, CE 2 = L and CE 2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes (1)
WRITE BYTE 1 (I/O[0:7], I/O P1 )
WRITE BYTE 2 (I/O[8:15], I/O P2 )
WRITE BYTE 3 (I/O[16:23], I/O P3 )
WRITE BYTE 4 (I/O[24:31], I/O P4 )
READ
WRITE ALL BYTES
NO WRITE
OPERATION
(2)
(2)
(2,3)
(2,3)
R/ W
H
L
L
L
L
L
L
BW 1
X
L
L
H
H
H
H
BW 2
X
L
H
L
H
H
H
BW 3 (3)
X
L
H
H
L
H
H
BW 4 (3)
X
L
H
H
H
L
H
5298 tbl 09
NOTES:
1. L = V IL , H = V IH , X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
Interleaved Burst Sequence Table ( LBO =V DD )
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
Second Address
Third Address
Fourth Address (1)
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
9
6.42
5298 tbl 10
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