参数资料
型号: IDT71V67903S75BG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/23页
文件大小: 0K
描述: IC SRAM 9MBIT 75NS 119BGA
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: SRAM - 同步
存储容量: 9M(512K x 18)
速度: 75ns
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
封装/外壳: 119-BGA
供应商设备封装: 119-PBGA(14x22)
包装: 带卷 (TR)
其它名称: 71V67903S75BG8
256K X 36, 512K X 18
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs, Single Cycle Deselect
IDT71V67703
IDT71V67903
256K x 36, 512K x 18 memory configurations
Supports fast access times:
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control ( GW ), byte write
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O supply (V DDQ )
Packaged in a JEDEC Standard 100-pin thin plastic quad
Features
x
x
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
x
x
enable ( BWE ), and byte writes ( BW x)
x
x
x
x
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA).
Description
The IDT71V67703/7903 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write,
Pin Description Summary
data, address and control registers. There are no registers in the data
output path (flow-through architecture). Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67703/7903 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected ( ADV =LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V67703/7903 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
A 0 -A 18
CE
CS 0 , CS 1
OE
GW
BWE
BW 1 , BW 2 , BW 3 , BW 4 (1)
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O 0 -I/O 31 , I/O P1 -I/O P4
V DD , V DDQ
V SS
NOTE:
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5309 tbl 01
1. BW 3 and BW 4 are not applicable for the IDT71V67903.
FEBRUARY 2009
DECEMBER 2003
1
?2002 Integrated Device Technology, Inc.
DSC-5309/05
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