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参数资料
| 型号： | IDT723643L12PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 1024X36 128QFP |
| 标准包装： | 72 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 36.8K（1K x 36） |
| 数据速率： | 83MHz |
| 访问时间： | 12ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723643L12PF |
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13
COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW
if a word in memory is the next data to be sent to the FlFO output register and
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
the time the word was written. The Empty Flag of the FIFO remains LOW until
the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing
the Empty Flag HIGH; only then can data be read.
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 10 and 11).
FULL/INPUT READY FLAGS (
FF/IR)
This is a dual purpose flag. In FWFT mode, the Input Ready (IR) function
is selected. In IDT Standard mode, the Full Flag (
FF) functionisselected. For
both timing modes, when the Full/Input Ready flag is HIGH, a memory location
is free in the FIFO to receive new data. No memory locations are free when the
Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array (CLKA). For both FWFT and IDT Standard modes, each
timeawordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock. Therefore,anFull/InputReadyflagisLOWiflessthantwo
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
nextmemorywritelocationhasbeenread. ThesecondLOW-to-HIGHtransition
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input
Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursattime
tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be
the first synchronization cycle (see Figures 13 and 14).
ALMOST-EMPTY FLAG (
AE)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
datafromitsarray(CLKB).ThestatemachinethatcontrolsanAlmost-Emptyflag
monitors a write pointer and read pointer comparator that indicates when the
FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.The
Almost-EmptystateisdefinedbythecontentsofregisterX.Theseregistersare
loaded with preset values during a FIFO reset, programmed from Port A, or
programmedserially(seeAlmost-EmptyflagandAlmost-Fullflagoffsetprogram-
ming section). An Almost-Empty flag is LOW when its FIFO contains X or less
words and is HIGH when its FIFO contains (X+1) or more words. Note that a
data word present in the FIFO output register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
offill.Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormorewords
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe
writethatfilledthememorytothe(X+1)level.AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO
writethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionofanAlmost-
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be the first synchro-
nization cycle. (See Figure 15).
ALMOST-FULL FLAG (
AF)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors a
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
statusisalmost-full,almost-full-1,oralmost-full-2.TheAlmost-Fullstateisdefined
by the contents of register Y. These registers are loaded with preset values
during a FlFO reset or, programmed from Port A, or programmed serially (see
Almost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection). AnAlmost-
Full flag is LOW when the number of words in its FIFO is greater than or equal
to(256-Y),(512-Y),or(1,024-Y)fortheIDT723623,IDT723633,orIDT723643
respectively. AnAlmost-FullflagisHIGHwhenthenumberofwordsinitsFIFO
is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the
IDT723623, IDT723633, or IDT723643 respectively. Note that a data word
present in the FIFO output register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
are required after a FIFO read for its Almost-Full flag to reflect the new level of
fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in memory to [256/
512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH
transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber
ofwordsinmemoryto[256/512/1,024-(Y+1)]. ALOW-to-HIGHtransitionofan
Almost-Full flag synchronizing clock begins the first synchronization cycle if it
occursattimetSKEW2orgreaterafterthereadthatreducesthenumberofwords
inmemoryto[256/512/1024-(Y+1)]. Otherwise,thesubsequentsynchronizing
clock cycle may be the first synchronization cycle. (See Figure 16).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723623/723633/723643 to
passcommandandcontrolinformationbetweenPortAandPortBwithoutputting
it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail
register and a FIFO for a port data transfer operation. The usable width of both
the Mail1 and Mail2 registers matches the selected bus size for Port B.
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen
aPortAwriteisselectedby
CSA,W/RA,andENAwithMBAHIGH. Iftheselected
Port B bus size is 36 bits, the usable width of the Mail1 register employs data
lines A0-A35. If the selected Port B bus size is 18 bits, then the usable width of
the Mail1 Register employs data lines A0-A17. (In this case, A18-A35 are don’t
care inputs.) If the selected Port B bus size is 9 bits, then the usable width of the
Mail1 Register employs data lines A0-A8. (In this case, A9-A35 are don’t care
inputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
Register when a Port B write is selected by
CSB, W/RB, and ENB with MBB
HIGH. If the selected Port B bus size is 36 bits, the usable width of the Mail2
employs data lines B0-B35. If the selected Port B bus size is 18 bits, then the
usablewidthoftheMail2RegisteremploysdatalinesB0-B17. (Inthiscase,B18-
B35aredon’tcareinputs.) IftheselectedPortBbussizeis9bits,thentheusable
widthoftheMail2RegisteremploysdatalinesB0-B8. (Inthiscase,B9-B35are
don’t care inputs.)
Writingdatatoamailregistersetsitscorrespondingflag(
MBF1orMBF2)
LOW. AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
FIFO output register when the port Mailbox Select input is LOW and from the
mail register when the port Mailbox Select input is HIGH.
TheMail1RegisterFlag(
MBF1)issetHIGHbyaLOW-to-HIGHtransition
on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with MBB
相关PDF资料 |
PDF描述 |
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| IDT723644L12PF | IC FIFO SYNC 2048X36 128QFP |
| IDT723646L12PF | IC FIFO SYNC 2048X36 128QFP |
| IDT723651L20PQFI | IC FIFO SYNC 2048X36 132QFP |
| IDT723653L15PF8 | IC FIFO SYNC 2048X36 128-TQFP |
| IDT723672L12PQF | IC FIFO SYNC 16384X36 132QFP |
相关代理商/技术参数 |
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| IDT723643L12PF8 | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723643L12PFG | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 128-Pin TQFP |
| IDT723643L15PF | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723643L15PF8 | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723644L12PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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