- 您现在的位置：买卖IC网 > PDF目录2076 > IDT723643L12PF (IDT, Integrated Device Technology Inc)IC FIFO SYNC 1024X36 128QFP PDF资料下载
参数资料
| 型号： | IDT723643L12PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/28页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 1024X36 128QFP |
| 标准包装： | 72 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 36.8K（1K x 36） |
| 数据速率： | 83MHz |
| 访问时间： | 12ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723643L12PF |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
14
COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35. For
an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this case,
B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on B0-B8. (In this case, B9-B35 are indeterminate.)
TheMail2RegisterFlag(
MBF2)issetHIGHbyaLOW-to-HIGHtransition
on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA
HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes only
whennewdataiswrittentotheregister. TheEndianSelectfeaturehasnoeffect
on mailbox data. For mail register and mail register flag timing diagrams, see
Figure 17 and 18.
BUS SIZING
The Port B bus can be configured in a 36-bit long word, 18-bit word, or
9-bit byte format for data read from the FIFO. The levels applied to the Port B
Bus Size Select (SIZE) and the Bus-Match Select (BM) determine the Port B
bus size. These levels should be static throughout FIFO operation. Both bus
sizeselectionsareimplementedatthecompletionofReset,bythetimetheFull/
Input Ready flag is set HIGH, as shown in Figure 2.
TwodifferentmethodsforsequencingdatatransferareavailableforPort
B when the bus size selection is either byte-or word-size. They are referred
to as Big-Endian (most significant byte first) and Little-Endian (least significant
bytefirst). ThelevelappliedtotheBig-EndianSelect(BE)inputduringtheLOW-
to-HIGH transition of
RS1selectstheendianmethodthatwillbeactiveduring
FIFO operation. BE is a don’t care input when the bus size selected for Port B
islongword.TheendianmethodisimplementedatthecompletionofReset,by
the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
Only 36-bit long word data is written to or read from the FIFO memory
on the IDT723623/723633/723643. Bus-matching operations are done after
data is read from the FIFO RAM. These bus-matching operations are not
available when transferring data via mailbox registers. Furthermore, both the
word-andbyte-sizebusselectionslimitthewidthofthedatabusthatcanbeused
for mail register operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The remaining data
outputswillbeindeterminate.Theremainingdatainputswillbedon’tcareinputs.
For example, when a word-size bus is selected, then mailbox data can be
transmitted only between A0-A17 and B0-B17. When a byte-size bus is
selected, then mailbox data can be transmitted only between A0-A8 and B0-
B8. (See Figures 17 and 18).
BUS-MATCHING FIFO READS
Data is read from the FIFO RAM in 36-bit long word increments. If a long
wordbussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFO
output register. If byte or word size is implemented on Port B, only the first one
ortwobytesappearontheselectedportionoftheFIFOoutputregister,withthe
restofthelongwordstoredinauxiliaryregisters. Inthiscase,subsequentFIFO
reads output the rest of the long word to the FIFO output register in the order
shown by Figure 2.
When reading data from FIFO in byte or word format, the unused B0-B35
outputsareindeterminate.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT723644L12PF | IC FIFO SYNC 2048X36 128QFP |
| IDT723646L12PF | IC FIFO SYNC 2048X36 128QFP |
| IDT723651L20PQFI | IC FIFO SYNC 2048X36 132QFP |
| IDT723653L15PF8 | IC FIFO SYNC 2048X36 128-TQFP |
| IDT723672L12PQF | IC FIFO SYNC 16384X36 132QFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT723643L12PF8 | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723643L12PFG | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 128-Pin TQFP |
| IDT723643L15PF | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723643L15PF8 | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723644L12PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
发布紧急采购，3分钟左右您将得到回复。