参数资料
型号: IDT72V261LA20PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 20/27页
文件大小: 0K
描述: IC FIFO SS 8192X18 20NS 64QFP
标准包装: 750
系列: 72V
功能: 同步
存储容量: 144K(8K x 18)
数据速率: 50MHz
访问时间: 20ns
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 72V261LA20PF8
27
3.3 VOLT CMOS SuperSync FIFO
16,384 x 9
32,768 x 9
IDT72V261LA
IDT72V271LA
ADDENDUM
DIFFERENCES BETWEEN THE IDT72V261LA/72V271LA AND IDT72V261L/72V271L
IDT has improved the performance of the IDT72V261/72V271 SuperSync FIFOs. The new versions are designated by the “LA” mark. The LA
part is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.
Item
NEW PART
OLD PART
Comments
IDT72V261LA
IDT72V261L
IDT72V271LA
IDT72V271L
Pin #3
DC (Don’t Care) - There is
FS (Frequency Select)
In the LA part this pin must be tied
no restriction on WCLK and
to either VCC or GND and must
RCLK. See note 1.
not toggle after reset.
First Word Latency
60ns(2) + tREF + 1 TRCLK(4)
tFWL
1 = 10*Tf
(3) + 2TRCLK(4)(ns)
First word latency in the LA part is
(IDT Standard Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
First Word Latency
60ns(2) + tREF + 2 TRCLK(4)
tFWL
2 = 10*Tf
(3) + 3TRCLK(4)(ns)
First word latency in the LA part is
(FWFT Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit Latency
60ns(2) + tREF + 1 TRCLK(4)
tRTF
1 = 14*Tf
(3) + 3TRCLK(4)(ns)
Retransmit latency in the LA part is
(IDT Standard Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit Latency
60ns(2) + tREF + 2 TRCLK(4)
tRTF
2 = 14*Tf
(3) + 4TRCLK(4)(ns)
Retransmit latency in the LA part is
(FWFT Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
ICC1
55mA
150mA
Active supply current
ICC2
20mA
15mA
Standby current
Typical ICC1(5)
10 + 0.95*fS + 0.02*CL*fS(mA)
Not Given
Typical ICC1 Current calculation
NOTES:
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.
2. This is tSKEW3.
3. Tf is the period of the ‘selected clock’.
4. TRCLK is the cycle period of the read clock.
5. Typical ICC1 is based on VCC = 3.3V, tA = 25
°C, fS = WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at fS/2, CL = Capacitive Load (in pF).
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
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