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| 型号： | IDT72V261LA20PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/27页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SS 8192X18 20NS 64QFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 144K（8K x 18） |
| 数据速率： | 50MHz |
| 访问时间： | 20ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V261LA20PF8 |
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IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 and 32,768 x 9
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 30, 2009
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data
setup and hold times must be met with respect to the LOW-to-HIGH
transition of the WCLK. It is permissible to stop the WCLK. Note that
while WCLK is idle, the
FF/IR, PAF and HF flags will not be updated.
(Note that WCLK is only capable of updating
HF flag to LOW.) The
Write and Read Clocks can either be independent or coincident.
WRITE ENABLE (
WEN)
When the
WEN input is LOW, data may be loaded into the FIFO
RAM array on the rising edge of every WCLK cycle if the device is not
full. Data is stored in the RAM array sequentially and independently of
any ongoing read operation.
When
WEN is HIGH, no new data is written in the RAM array on
each WCLK cycle.
To prevent data overflow in the IDT Standard mode,
FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read
cycle,
FF will go HIGH allowing a write to occur. The FF is updated by
two WCLK cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode,
IR will go HIGH,
inhibiting further write operations. Upon the completion of a valid read
cycle,
IR will go LOW allowing a write to occur. The IR flag is updated
by two WCLK cycles + tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data
can be read on the outputs, on the rising edge of the RCLK input. It is
permissible to stop the RCLK. Note that while RCLK is idle, the
EF/OR,
PAE and HF flags will not be updated. (Note that RCLK is only capable
of updating the
HF flag to HIGH.) The Write and Read Clocks can be
independent or coincident.
READ ENABLE (
REN)
When Read Enable is LOW, data is loaded from the RAM array into
the output register on the rising edge of every RCLK cycle if the device
is not empty.
When the
REN input is HIGH, the output register holds the previous
data and no new data is loaded into the output register. The data
outputs Q0-Qn maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the
first word written to an empty FIFO, must be requested using
REN.
When the last word has been read from the FIFO, the Empty Flag (
EF)
will go LOW, inhibiting further read operations.
REN is ignored when
the FIFO is empty. Once a write is performed,
EF will go HIGH allowing
a read to occur. The
EF flag is updated by two RCLK cycles + tSKEW
after the valid WCLK cycle.
In the FWFT mode, the first word written to an empty FIFO automati-
cally goes to the outputs Qn, on the third valid LOW to HIGH transition
of RCLK + tSKEW after the first write.
REN does not need to be
asserted LOW. In order to access all other words, a read must be
executed using
REN. The RCLK LOW to HIGH transition after the last
word has been read from the FIFO, Output Ready (
OR) will go HIGH
with a true read (RCLK with
REN = LOW), inhibiting further read opera-
tions.
REN is ignored when the FIFO is empty.
SERIAL ENABLE (
SEN)
The
SEN input is an enable used only for serial programming of the
offset registers. The serial programming method must be selected
during Master Reset.
SEN is always used in conjunction with LD.
When these lines are both LOW, data at the SI input can be loaded into
the program register one bit for each LOW-to-HIGH transition of WCLK.
(See Figure 4.)
When
SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded.
SEN functions the same way in
both IDT Standard and FWFT modes.
OUTPUT ENABLE (
OE)
When Output Enable is enabled (LOW), the parallel output buffers
receive data from the output register. When
OE is HIGH, the output
data bus (Qn) goes into a high impedance state.
LOAD (
LD)
This is a dual purpose pin. During Master Reset, the state of the
LD
input determines one of two default offset values (127 or 1,023) for the
PAE and PAF flags, along with the method by which these offset regis-
ters can be programmed, parallel or serial. After Master Reset,
LD
enables write operations to and read operations from the offset regis-
ters. Only the offset loading method currently selected can be used to
write to the registers. Offset registers can be read only in parallel. A
LOW on
LD during Master Reset selects a default PAE offset value of
07FH (a threshold 127 words from the empty boundary), a default
PAF
offset value of 07FH (a threshold 127 words from the full boundary),
and parallel loading of other offset values. A HIGH on
LD during
Master Reset selects a default
PAE offset value of 3FFH (a threshold
1,023 words from the empty boundary), a default
PAF offset value of
3FFH (a threshold 1,023 words from the full boundary), and serial load-
ing of other offset values.
After Master Reset, the
LD pin is used to activate the programming
process of the flag offset values
PAE and PAF. Pulling LD LOW will
begin a serial loading or parallel load or read of these offset values.
See Figure 4, Programmable Flag Offset Programming Sequence.
OUTPUTS:
FULL FLAG (
FF/IR)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FF)
function is selected. When the FIFO is full,
FF will go LOW, inhibiting
further write operations. When
FF is HIGH, the FIFO is not full. If no
reads are performed after a reset (either
MRS or PRS), FF will go LOW
after D writes to the FIFO (D = 16,384 for the IDT72V261LA and 32,768
for the IDT72V271LA). See Figure 7, Write Cycle and Full Flag Timing
(IDT Standard Mode), for the relevant timing information.
In FWFT mode, the Input Ready (
IR) function is selected. IR goes
LOW when memory space is available for writing in data. When there
is no longer any free space left,
IR goes HIGH, inhibiting further write
operations. If no reads are performed after a reset (either
MRS or
PRS), IR will go HIGH after D writes to the FIFO (D = 16,385 for the
IDT72V261LA and 32,769 for the IDT72V271LA) See Figure 9, Write
Timing (FWFT Mode), for the relevant timing information.
The
IR status not only measures the contents of the FIFO memory,
but also counts the presence of a word in the output register. Thus, in
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| IDT72V261LA20TF | 功能描述:IC FIFO SS 8192X18 20NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V261LA20TF8 | 功能描述:IC FIFO SS 8192X18 20NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V263L10PF | 功能描述:IC FIFO 8192X18 10NS 80QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V263L10PF8 | 功能描述:IC FIFO 8192X18 10NS 80QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V263L10PFI | 功能描述:IC FIFO 8192X18 10NS 80QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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