参数资料
型号: IDT72V36110L7-5PFGI
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/48页
文件大小: 0K
描述: 3.3V SUPERSYNC II 36BIT FIFO
标准包装: 36
系列: 72V
功能: 同步
存储容量: 4.7M(131K x 36)
数据速率: 166MHz
访问时间: 5ns
电源电压: 3.15 V ~ 3.45 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-TQFP(14x20)
包装: 托盘
其它名称: 800-2593
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting
OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When
ORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
the first word appears on the outputs, no LOW on
RENisnecessary.Reading
all subsequent words requires a LOW on
REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
For either IDT Standard mode or FWFT mode, updating of the
PAE, HF
and
PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafter
RTissetup,
the
PAEflagwillbeupdated. HFisasynchronous,thustherisingedgeofRCLK
that
RTissetupwillupdateHF. PAFissynchronizedtoWCLK,thusthesecond
rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that
RT
is setup will update
PAF. RT is synchronized to RCLK.
The Retransmit function has the option of two modes of operation, either
“normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned
previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero
latency” retransmit operation. Zero latency basically means that the first data
word to be retransmitted, is placed onto the output register with respect to the
RCLK pulse that initiated the retransmit.
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