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| 型号： | IDT72V36110L7-5PFGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 4/48页 |
| 文件大小： | 0K |
| 描述： | 3.3V SUPERSYNC II 36BIT FIFO |
| 标准包装： | 36 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7M（131K x 36） |
| 数据速率： | 166MHz |
| 访问时间： | 5ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 800-2593 |
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12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
to the FIFO. D = 65,536 writes for the IDT72V36100 and 131,072 writes for
the IDT72V36110, respectively.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequentreadoperationswillcause
PAFandHFtogoHIGHattheconditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
When the last word has been read from the FIFO, the
EFwillgoLOWinhibiting
further read operations.
REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the
EFandFFoutputsaredouble
register-bufferedoutputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
7,8,11 and 13.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO,
WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitions of WCLK. After the first write is performed, the Output Ready (
OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO.
PAEwillgo
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offsetvalue.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the
HFwouldtoggletoLOWoncethe32,770th
word for the IDT72V36100 and 65,538th word for the IDT72V36110, respec-
tivelywaswrittenintotheFIFO. ContinuingtowritedataintotheFIFOwillcause
the
PAF to go LOW. Again, if no reads are performed, the PAF will go LOW
after (65,537-m) writes for the IDT72V36100 and (131,073-m) writes for the
IDT72V36110, where m is the full offset value. The default setting for these
values are stated in the footnote of Table 2.
WhentheFIFOisfull,theInputReady(
IR)flagwillgoHIGH,inhibitingfurther
write operations. If no reads are performed after a reset,
IR willgoHIGHafter
D writes to the FIFO. D = 65,537 writes for the IDT72V36100 and 131,073
writesfortheIDT72V36110,respectively.NotethattheadditionalwordinFWFT
mode is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the
IR flag to go LOW.
Subsequent read operations will cause the
PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations,the
PAEwillgoLOWwhentherearen+1wordsintheFIFO,where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO,
OR will go
HIGHinhibitingfurtherreadoperations.
RENisignoredwhentheFIFOisempty.
When configured in FWFT mode, the
OR flag output is triple register-
buffered, and the
IRflag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10, 12,
and 14.
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V36100/72V36110 support two different timing modes of
operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selectionofwhichmodewilloperateisdeterminedduringMasterReset,bythe
state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(
FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR)toindicatewhetherornotthere
is valid data at the data outputs (Qn). It also uses Input Ready (
IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,
REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (
REN) and RCLK.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (
WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (
EF)willgoHIGH.Subsequentwriteswillcontinue
to fill up the FIFO. The Programmable Almost-Empty flag (
PAE)willgoHIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(
HF)wouldtoggletoLOWonce
the32,769thwordfortheIDT72V36100and65,537thwordfortheIDT72V36110,
respectively was written into the FIFO. Continuing to write data into the FIFO
will cause the Programmable Almost-Full flag (
PAF) to go LOW. Again, if no
reads are performed, the
PAF will go LOW after (65,536-m) writes for the
IDT72V36100 and (131,072-m) writes for the IDT72V36110. The offset “m”
isthefulloffsetvalue.Thedefaultsettingforthesevaluesarestatedinthefootnote
of Table 2. This parameter is also user programmable. See section on
Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (
FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,
FFwillgoLOWafterDwrites
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| IDT72V36110L7-5PFI | 功能描述:IC FIFO 131KX36 7-5NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3611L12PQF | 制造商:Integrated Device Technology Inc 功能描述:72V3611L12PQF |
| IDT72V3611L15PF | 功能描述:IC FIFO SYNC 64X36 15NS 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3611L15PF8 | 功能描述:IC FIFO SYNC 64X36 15NS 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3611L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
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