参数资料
型号: IDT72V3631L20PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/21页
文件大小: 0K
描述: IC SYNCFIFO 512X36 20NS 120-TQFP
标准包装: 750
系列: 72V
功能: 异步,同步
存储容量: 18.4K(512 x 36)
数据速率: 520Mbs
访问时间: 20ns
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 120-LQFP
供应商设备封装: 120-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 72V3631L20PF8
18
COMMERCIALTEMPERATURERANGE
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO 512 x 36, 1,024 x 36 and 2,048 x 36
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Figure 13. IR Timing from the End of Retransmit Mode when One or More Write Locations are Available
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for
AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then
AF may transition HIGH one CLKA cycle later than shown.
2. Depth is 512 for the IDT72V3631, 1,024 for the IDT72V3641, and 2,048 for the IDT72V3651.
3. Y is the value loaded in the Almost-Full flag Offset register.
Figure 14.
AF
AF Timing from the End of Retransmit Mode when (Y+1) or More Write Locations are Available
Figure 15. Timing for Mail1 Register and
MBF1
MBF1 Flag
tSKEW1
CLKA
IR
CLKB
RTM
FIFO Filled to First Restransmit Word
1
2
One or More Write Locations Available
4658 drw 16
(1)
tPIR
tRMS
tRMH
CLKA
AF
CLKB
RTM
tSKEW2
(Depth
-Y) or More Words Past First Restransmit Word
1
2
(Y+1) or More Write Locations Available
4658 drw 17
(1)
tPAE
tRMS
tRMH
(2)
4658 drw 18
CLKA
ENA
A0 - A35
MBA
CSA
W/
RA
CLKB
MBF1
CSB
MBB
ENB
B0 - B35
W/RB
W1
tENS2
tENH2
tDS
tDH
tPMF
tEN
tMDV
tPMR
tENS1
tENH1
tDIS
W1 (Remains valid in Mail1 Register after read)
FIFO Output Register
tENS2
tENH2
tENS2
tENH2
tENS2
tENH2
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